xHCI
include/drivers/usb/xhci.h View source View on GitHubStructs
Section titled “Structs”xhci_cap_regs
Section titled “xhci_cap_regs”struct xhci_cap_regs {
uint8_t cap_length;
uint8_t reserved;
uint16_t hci_version;
uint32_t hcs_params1;
uint32_t hcs_params2;
uint32_t hcs_params3;
uint32_t hcc_params1;
uint32_t dboff;
uint32_t rtsoff;
uint32_t hcc_params2;
};xhci_port_regs
Section titled “xhci_port_regs”struct xhci_port_regs {
uint32_t portsc;
uint32_t portpmsc;
uint32_t portli;
uint32_t portct;
};xhci_usbcmd
Section titled “xhci_usbcmd”struct xhci_usbcmd {
union {
uint32_t raw;
struct {
uint32_t run_stop : 1;
uint32_t host_controller_reset : 1;
uint32_t interrupter_enable : 1;
uint32_t host_system_error_en : 1;
uint32_t reserved0 : 3;
uint32_t light_host_controller_reset : 1;
uint32_t controller_save_state : 1;
uint32_t controller_restore_state : 1;
uint32_t enable_wrap_event : 1;
uint32_t enable_u3_mf_index : 1;
uint32_t reserved1 : 1;
uint32_t cem_enable : 1;
uint32_t extended_tbc_enable : 1;
uint32_t extended_tbc_trb_status_enable : 1;
uint32_t vtio_enable : 1;
uint32_t reserved2 : 15;
};
};
};xhci_slot_ctx
Section titled “xhci_slot_ctx”struct xhci_slot_ctx {
uint32_t route_string : 20;
uint32_t speed : 4;
uint32_t reserved0 : 1;
uint32_t mtt : 1;
uint32_t hub : 1;
uint32_t context_entries : 5;
uint32_t max_exit_latency : 16;
uint32_t root_hub_port : 8;
uint32_t num_ports : 8;
uint32_t parent_hub_slot_id : 8;
uint32_t parent_port_number : 8;
uint32_t parent_think_time : 2;
uint32_t reserved1 : 4;
uint32_t interrupter_target : 10;
uint32_t usb_device_address : 8;
uint32_t reserved2 : 19;
uint32_t slot_state : 5;
uint32_t reserved3[4];
};xhci_ep_ctx
Section titled “xhci_ep_ctx”struct xhci_ep_ctx {
uint32_t ep_state : 3;
uint32_t reserved1 : 5;
uint32_t mult : 2;
uint32_t max_pstreams : 5;
uint32_t lsa : 1;
uint32_t interval : 8;
uint32_t max_esit_payload_hi : 8;
uint32_t reserved2 : 1;
uint32_t error_count : 2;
uint32_t ep_type : 3;
uint32_t reserved3 : 1;
uint32_t host_initiate_disable : 1;
uint32_t max_burst_size : 8;
uint32_t max_packet_size : 16;
union {
uint64_t dequeue_ptr_raw;
struct {
uint32_t dcs : 1;
uint32_t reserved4 : 3;
uint64_t dequeue_ptr : 60;
};
};
uint32_t average_trb_length : 16;
uint32_t max_esit_payload_lo : 16;
uint32_t reserved5[3];
};xhci_input_ctrl_ctx
Section titled “xhci_input_ctrl_ctx”struct xhci_input_ctrl_ctx {
uint32_t drop_flags;
uint32_t add_flags;
uint32_t reserved[5];
uint32_t config : 8;
uint32_t interface_num : 8;
uint32_t alternate_setting : 8;
uint32_t reserved1 : 8;
};xhci_input_ctx
Section titled “xhci_input_ctx”struct xhci_input_ctx {
struct xhci_input_ctrl_ctx ctrl_ctx;
struct xhci_slot_ctx slot_ctx;
struct xhci_ep_ctx ep_ctx[31];
};xhci_device_ctx
Section titled “xhci_device_ctx”struct xhci_device_ctx {
struct xhci_slot_ctx slot_ctx;
struct xhci_ep_ctx ep_ctx[32];
};xhci_op_regs
Section titled “xhci_op_regs”struct xhci_op_regs {
struct xhci_usbcmd usbcmd;
uint32_t usbsts;
uint32_t pagesize;
uint32_t reserved[2];
uint32_t dnctrl;
uint64_t crcr;
uint32_t reserved2[4];
uint64_t dcbaap;
uint32_t config;
uint32_t reserved3[241];
struct xhci_port_regs regs[];
};xhci_trb
Section titled “xhci_trb”struct xhci_trb {
uint64_t parameter;
uint32_t status;
uint32_t control;
};xhci_ring
Section titled “xhci_ring”struct xhci_ring {
struct xhci_trb *trbs;
uint64_t phys;
uint32_t enqueue_index;
uint32_t dequeue_index;
uint8_t cycle;
uint32_t size;
size_t outgoing;
};xhci_erst_entry
Section titled “xhci_erst_entry”struct xhci_erst_entry {
uint64_t ring_segment_base;
uint32_t ring_segment_size;
uint32_t reserved;
};xhci_interrupter_regs
Section titled “xhci_interrupter_regs”struct xhci_interrupter_regs {
uint32_t iman;
uint32_t imod;
uint32_t erstsz;
uint32_t reserved;
uint64_t erstba;
uint64_t erdp;
};xhci_dcbaa
Section titled “xhci_dcbaa”struct xhci_dcbaa {
uint64_t ptrs[256];
};xhci_ext_cap
Section titled “xhci_ext_cap”struct xhci_ext_cap {
uint8_t cap_id;
uint8_t next;
uint16_t cap_specific;
};xhci_slot
Section titled “xhci_slot”struct xhci_slot {
_Atomic enum xhci_slot_state state;
struct xhci_device *dev;
struct xhci_ring *ep_rings[32];
uint8_t slot_id;
refcount_t refcount;
struct xhci_port *port;
struct usb_device *udev;
};xhci_port
Section titled “xhci_port”struct xhci_port {
struct spinlock update_lock;
uint8_t port_id;
struct xhci_slot *slot;
uint8_t speed;
bool usb3;
uint64_t generation;
enum xhci_port_state state;
struct xhci_device *dev;
};xhci_device
Section titled “xhci_device”struct xhci_device {
irq_t irq;
struct pci_device *pci;
struct xhci_input_ctx *input_ctx;
struct xhci_cap_regs *cap_regs;
struct xhci_op_regs *op_regs;
struct xhci_interrupter_regs *intr_regs;
struct xhci_dcbaa *dcbaa;
struct xhci_ring *event_ring;
struct xhci_ring *cmd_ring;
struct xhci_erst_entry *erst;
struct xhci_port_regs *port_regs;
uint64_t ports;
struct xhci_slot slots[XHCI_SLOT_COUNT];
struct xhci_port port_info[XHCI_PORT_COUNT];
struct list_head requests[XHCI_REQ_LIST_MAX];
size_t num_devices;
struct list_head devices;
struct spinlock lock;
struct semaphore sem;
struct semaphore port_disconnect;
struct semaphore port_connect;
struct usb_controller *controller;
atomic_bool worker_waiting;
};xhci_command
Section titled “xhci_command”struct xhci_command {
struct xhci_ring *ring;
struct xhci_slot *slot;
uint32_t ep_id;
size_t num_trbs;
void (*emit)(struct xhci_command *cmd, struct xhci_ring *ring);
struct xhci_request *request;
void *private;
};xhci_request
Section titled “xhci_request”struct xhci_request {
enum xhci_request_command_type type;
enum xhci_request_list list_owner;
struct usb_request *urb;
struct xhci_command *command;
struct xhci_trb *last_trb;
uint64_t trb_phys;
uint8_t port;
volatile uint8_t completion_code;
volatile uint64_t return_parameter;
volatile uint32_t return_status;
volatile uint32_t return_control;
uint64_t generation;
volatile enum xhci_request_status status;
struct list_head list;
void (*callback)(struct xhci_device *, struct xhci_request *);
void *private;
};xhci_return
Section titled “xhci_return”struct xhci_return {
uint32_t control;
uint32_t status;
};xhci_slot_state
Section titled “xhci_slot_state”enum xhci_slot_state {
XHCI_SLOT_STATE_UNDEF,
XHCI_SLOT_STATE_ENABLED,
XHCI_SLOT_STATE_DISCONNECTING,
XHCI_SLOT_STATE_DISCONNECTED,
};xhci_port_state
Section titled “xhci_port_state”enum xhci_port_state {
XHCI_PORT_STATE_UNDEF,
XHCI_PORT_STATE_CONNECTING,
XHCI_PORT_STATE_CONNECTED,
XHCI_PORT_STATE_DISCONNECTING,
XHCI_PORT_STATE_DISCONNECTED,
};xhci_request_status
Section titled “xhci_request_status”enum xhci_request_status {
XHCI_REQUEST_SENDING,
XHCI_REQUEST_OK,
XHCI_REQUEST_CANCELLED,
XHCI_REQUEST_DISCONNECT,
XHCI_REQUEST_ERR,
};xhci_request_list
Section titled “xhci_request_list”enum xhci_request_list {
XHCI_REQ_LIST_NONE,
XHCI_REQ_LIST_OUTGOING,
XHCI_REQ_LIST_WAITING,
XHCI_REQ_LIST_PROCESSED,
XHCI_REQ_LIST_MAX,
};xhci_request_command_type
Section titled “xhci_request_command_type”enum xhci_request_command_type {
XHCI_CMD_TYPE_NONE,
XHCI_CMD_TYPE_ENABLE_SLOT,
XHCI_CMD_TYPE_DISABLE_SLOT,
XHCI_CMD_TYPE_ADDRESS_DEVICE,
XHCI_CMD_TYPE_CONFIGURE_ENDPOINT,
XHCI_CMD_TYPE_EVALUATE_CONTEXT,
XHCI_CMD_TYPE_RESET_ENDPOINT,
XHCI_CMD_TYPE_STOP_ENDPOINT,
XHCI_CMD_TYPE_SET_TR_DEQUEUE_POINTER,
XHCI_CMD_TYPE_RESET_DEVICE,
XHCI_CMD_TYPE_FORCE_EVENT,
XHCI_CMD_TYPE_INTERRUPT_TRANSFER,
XHCI_CMD_TYPE_CONTROL_TRANSFER,
XHCI_CMD_TYPE_NO_OP,
XHCI_CMD_TYPE_NORMAL,
};Functions
Section titled “Functions”xhci_slot_state_str
Section titled “xhci_slot_state_str”char xhci_slot_state_str(enum xhci_slot_state s);xhci_port_state_str
Section titled “xhci_port_state_str”char xhci_port_state_str(enum xhci_port_state s);xhci_request_command_type_str
Section titled “xhci_request_command_type_str”char xhci_request_command_type_str(enum xhci_request_command_type t);xhci_init
Section titled “xhci_init”void xhci_init(uint8_t bus, uint8_t slot, uint8_t func, struct pci_device *dev);Macros
Section titled “Macros”XHCI_DEVICE_TIMEOUT
Section titled “XHCI_DEVICE_TIMEOUT”#define XHCI_DEVICE_TIMEOUT 1000TRB_RING_SIZE
Section titled “TRB_RING_SIZE”#define TRB_RING_SIZE 256XHCI_PORT_COUNT
Section titled “XHCI_PORT_COUNT”#define XHCI_PORT_COUNT 64XHCI_SLOT_COUNT
Section titled “XHCI_SLOT_COUNT”#define XHCI_SLOT_COUNT 255XHCI_INPUT_CTX_ADD_FLAGS
Section titled “XHCI_INPUT_CTX_ADD_FLAGS”#define XHCI_INPUT_CTX_ADD_FLAGS ((1 << 0) | (1 << 1))XHCI_SETUP_TRANSFER_TYPE_NONE
Section titled “XHCI_SETUP_TRANSFER_TYPE_NONE”#define XHCI_SETUP_TRANSFER_TYPE_NONE 0XHCI_SETUP_TRANSFER_TYPE_OUT
Section titled “XHCI_SETUP_TRANSFER_TYPE_OUT”#define XHCI_SETUP_TRANSFER_TYPE_OUT 2XHCI_SETUP_TRANSFER_TYPE_IN
Section titled “XHCI_SETUP_TRANSFER_TYPE_IN”#define XHCI_SETUP_TRANSFER_TYPE_IN 3XHCI_USBSTS_HCH
Section titled “XHCI_USBSTS_HCH”#define XHCI_USBSTS_HCH 1 /* HC halted */XHCI_USBSTS_HSE
Section titled “XHCI_USBSTS_HSE”#define XHCI_USBSTS_HSE (1 << 2) /* host system error */XHCI_USBSTS_EI
Section titled “XHCI_USBSTS_EI”#define XHCI_USBSTS_EI (1 << 3) /* event interrupt */XHCI_USBSTS_PCD
Section titled “XHCI_USBSTS_PCD”#define XHCI_USBSTS_PCD (1 << 4) /* port change detect */XHCI_IMAN_MASK
Section titled “XHCI_IMAN_MASK”#define XHCI_IMAN_MASK 0x2XHCI_IMAN_INT_PENDING
Section titled “XHCI_IMAN_INT_PENDING”#define XHCI_IMAN_INT_PENDING 0x1XHCI_IMAN_INT_ENABLE
Section titled “XHCI_IMAN_INT_ENABLE”#define XHCI_IMAN_INT_ENABLE 0x2XHCI_ENDPOINT_TYPE_INVAL
Section titled “XHCI_ENDPOINT_TYPE_INVAL”#define XHCI_ENDPOINT_TYPE_INVAL 0XHCI_ENDPOINT_TYPE_ISOCH_OUT
Section titled “XHCI_ENDPOINT_TYPE_ISOCH_OUT”#define XHCI_ENDPOINT_TYPE_ISOCH_OUT 1XHCI_ENDPOINT_TYPE_BULK_OUT
Section titled “XHCI_ENDPOINT_TYPE_BULK_OUT”#define XHCI_ENDPOINT_TYPE_BULK_OUT 2XHCI_ENDPOINT_TYPE_INTERRUPT_OUT
Section titled “XHCI_ENDPOINT_TYPE_INTERRUPT_OUT”#define XHCI_ENDPOINT_TYPE_INTERRUPT_OUT 3XHCI_ENDPOINT_TYPE_CONTROL_BI
Section titled “XHCI_ENDPOINT_TYPE_CONTROL_BI”#define XHCI_ENDPOINT_TYPE_CONTROL_BI 4XHCI_ENDPOINT_TYPE_ISOCH_IN
Section titled “XHCI_ENDPOINT_TYPE_ISOCH_IN”#define XHCI_ENDPOINT_TYPE_ISOCH_IN 5XHCI_ENDPOINT_TYPE_BULK_IN
Section titled “XHCI_ENDPOINT_TYPE_BULK_IN”#define XHCI_ENDPOINT_TYPE_BULK_IN 6XHCI_ENDPOINT_TYPE_INTERRUPT_IN
Section titled “XHCI_ENDPOINT_TYPE_INTERRUPT_IN”#define XHCI_ENDPOINT_TYPE_INTERRUPT_IN 7XHCI_EXT_CAP_ID_LEGACY_SUPPORT
Section titled “XHCI_EXT_CAP_ID_LEGACY_SUPPORT”#define XHCI_EXT_CAP_ID_LEGACY_SUPPORT 1XHCI_EXT_CAP_ID_USB
Section titled “XHCI_EXT_CAP_ID_USB”#define XHCI_EXT_CAP_ID_USB 2TRB_TYPE_RESERVED
Section titled “TRB_TYPE_RESERVED”#define TRB_TYPE_RESERVED 0x00TRB_TYPE_NORMAL
Section titled “TRB_TYPE_NORMAL”#define TRB_TYPE_NORMAL 0x01TRB_TYPE_SETUP_STAGE
Section titled “TRB_TYPE_SETUP_STAGE”#define TRB_TYPE_SETUP_STAGE 0x02TRB_TYPE_DATA_STAGE
Section titled “TRB_TYPE_DATA_STAGE”#define TRB_TYPE_DATA_STAGE 0x03TRB_TYPE_STATUS_STAGE
Section titled “TRB_TYPE_STATUS_STAGE”#define TRB_TYPE_STATUS_STAGE 0x04TRB_TYPE_ISOCH
Section titled “TRB_TYPE_ISOCH”#define TRB_TYPE_ISOCH 0x05TRB_TYPE_LINK
Section titled “TRB_TYPE_LINK”#define TRB_TYPE_LINK 0x06TRB_TYPE_EVENT_DATA
Section titled “TRB_TYPE_EVENT_DATA”#define TRB_TYPE_EVENT_DATA 0x07TRB_TYPE_NO_OP
Section titled “TRB_TYPE_NO_OP”#define TRB_TYPE_NO_OP 0x08TRB_TYPE_NO_OP_COMMAND
Section titled “TRB_TYPE_NO_OP_COMMAND”#define TRB_TYPE_NO_OP_COMMAND 0x8TRB_TYPE_ENABLE_SLOT
Section titled “TRB_TYPE_ENABLE_SLOT”#define TRB_TYPE_ENABLE_SLOT 0x09TRB_TYPE_DISABLE_SLOT
Section titled “TRB_TYPE_DISABLE_SLOT”#define TRB_TYPE_DISABLE_SLOT 0x0ATRB_TYPE_ADDRESS_DEVICE
Section titled “TRB_TYPE_ADDRESS_DEVICE”#define TRB_TYPE_ADDRESS_DEVICE 0x0BTRB_TYPE_CONFIGURE_ENDPOINT
Section titled “TRB_TYPE_CONFIGURE_ENDPOINT”#define TRB_TYPE_CONFIGURE_ENDPOINT 0x0CTRB_TYPE_EVALUATE_CONTEXT
Section titled “TRB_TYPE_EVALUATE_CONTEXT”#define TRB_TYPE_EVALUATE_CONTEXT 0x0DTRB_TYPE_RESET_ENDPOINT
Section titled “TRB_TYPE_RESET_ENDPOINT”#define TRB_TYPE_RESET_ENDPOINT 0x0ETRB_TYPE_STOP_ENDPOINT
Section titled “TRB_TYPE_STOP_ENDPOINT”#define TRB_TYPE_STOP_ENDPOINT 0x0FTRB_TYPE_SET_TR_DEQUEUE_POINTER
Section titled “TRB_TYPE_SET_TR_DEQUEUE_POINTER”#define TRB_TYPE_SET_TR_DEQUEUE_POINTER 0x10TRB_TYPE_RESET_DEVICE
Section titled “TRB_TYPE_RESET_DEVICE”#define TRB_TYPE_RESET_DEVICE 0x11TRB_TYPE_FORCE_EVENT
Section titled “TRB_TYPE_FORCE_EVENT”#define TRB_TYPE_FORCE_EVENT 0x12TRB_TYPE_NEGOTIATE_BW
Section titled “TRB_TYPE_NEGOTIATE_BW”#define TRB_TYPE_NEGOTIATE_BW 0x13TRB_TYPE_SET_LATENCY_TOLERANCE
Section titled “TRB_TYPE_SET_LATENCY_TOLERANCE”#define TRB_TYPE_SET_LATENCY_TOLERANCE 0x14TRB_TYPE_GET_PORT_BANDWIDTH
Section titled “TRB_TYPE_GET_PORT_BANDWIDTH”#define TRB_TYPE_GET_PORT_BANDWIDTH 0x15TRB_TYPE_FORCE_HEADER
Section titled “TRB_TYPE_FORCE_HEADER”#define TRB_TYPE_FORCE_HEADER 0x16TRB_TYPE_NO_OP_2_COMMAND
Section titled “TRB_TYPE_NO_OP_2_COMMAND”#define TRB_TYPE_NO_OP_2_COMMAND 0x17TRB_TYPE_TRANSFER_EVENT
Section titled “TRB_TYPE_TRANSFER_EVENT”#define TRB_TYPE_TRANSFER_EVENT 0x20TRB_TYPE_COMMAND_COMPLETION
Section titled “TRB_TYPE_COMMAND_COMPLETION”#define TRB_TYPE_COMMAND_COMPLETION 0x21TRB_TYPE_PORT_STATUS_CHANGE
Section titled “TRB_TYPE_PORT_STATUS_CHANGE”#define TRB_TYPE_PORT_STATUS_CHANGE 0x22TRB_TYPE_BANDWIDTH_REQUEST
Section titled “TRB_TYPE_BANDWIDTH_REQUEST”#define TRB_TYPE_BANDWIDTH_REQUEST 0x23TRB_TYPE_DOORBELL_EVENT
Section titled “TRB_TYPE_DOORBELL_EVENT”#define TRB_TYPE_DOORBELL_EVENT 0x24TRB_TYPE_HOST_CONTROLLER_EVENT
Section titled “TRB_TYPE_HOST_CONTROLLER_EVENT”#define TRB_TYPE_HOST_CONTROLLER_EVENT 0x25TRB_TYPE_DEVICE_NOTIFICATION
Section titled “TRB_TYPE_DEVICE_NOTIFICATION”#define TRB_TYPE_DEVICE_NOTIFICATION 0x26TRB_TYPE_MFINDEX_WRAP
Section titled “TRB_TYPE_MFINDEX_WRAP”#define TRB_TYPE_MFINDEX_WRAP 0x27TRB_FIELD
Section titled “TRB_FIELD”#define TRB_FIELD(val, lo, hi) BIT_RANGE(val, lo, hi)TRB_TYPE
Section titled “TRB_TYPE”#define TRB_TYPE(ctrl) TRB_FIELD(ctrl, 10, 15)TRB_SLOT
Section titled “TRB_SLOT”#define TRB_SLOT(ctrl) TRB_FIELD(ctrl, 24, 31)TRB_EP
Section titled “TRB_EP”#define TRB_EP(ctrl) TRB_FIELD(ctrl, 16, 23)TRB_CC
Section titled “TRB_CC”#define TRB_CC(status) TRB_FIELD(status, 24, 31)TRB_PORT
Section titled “TRB_PORT”#define TRB_PORT(parameter) TRB_FIELD(parameter, 24, 31)TRB_SET_TYPE
Section titled “TRB_SET_TYPE”#define TRB_SET_TYPE(val) (((val) & 0x3F) << 10)TRB_SET_CYCLE
Section titled “TRB_SET_CYCLE”#define TRB_SET_CYCLE(val) (((val) & 1))TRB_SET_INTERRUPTER_TARGET
Section titled “TRB_SET_INTERRUPTER_TARGET”#define TRB_SET_INTERRUPTER_TARGET(target) ((target) >> 21)TRB_CYCLE_BIT
Section titled “TRB_CYCLE_BIT”#define TRB_CYCLE_BIT (1 << 0)TRB_ENT_BIT
Section titled “TRB_ENT_BIT”#define TRB_ENT_BIT (1 << 1) // Evaluate Next TRBTRB_ISP_BIT
Section titled “TRB_ISP_BIT”#define TRB_ISP_BIT (1 << 2) // Interrupt on Short PacketTRB_NS_BIT
Section titled “TRB_NS_BIT”#define TRB_NS_BIT (1 << 3) // No SnoopTRB_CH_BIT
Section titled “TRB_CH_BIT”#define TRB_CH_BIT (1 << 4) // ChainTRB_IOC_BIT
Section titled “TRB_IOC_BIT”#define TRB_IOC_BIT (1 << 5) // Interrupt On CompletionTRB_IDT_BIT
Section titled “TRB_IDT_BIT”#define TRB_IDT_BIT (1 << 6) // Immediate DataTRB_BEI_BIT
Section titled “TRB_BEI_BIT”#define TRB_BEI_BIT (1 << 9) // Block Event Interrupt (ISO)TRB_TOGGLE_CYCLE_BIT
Section titled “TRB_TOGGLE_CYCLE_BIT”#define TRB_TOGGLE_CYCLE_BIT (1 << 1)TRB_TYPE_SHIFT
Section titled “TRB_TYPE_SHIFT”#define TRB_TYPE_SHIFT 10TRB_SET_SLOT_ID
Section titled “TRB_SET_SLOT_ID”#define TRB_SET_SLOT_ID(id) (((id) & 0xFF) << 24)PORTSC_CCS
Section titled “PORTSC_CCS”#define PORTSC_CCS (1 << 0) // Current Connect StatusPORTSC_PED
Section titled “PORTSC_PED”#define PORTSC_PED (1 << 1) // Port Enabled/DisabledPORTSC_OCA
Section titled “PORTSC_OCA”#define PORTSC_OCA (1 << 3) // Over-Current ActivePORTSC_RESET
Section titled “PORTSC_RESET”#define PORTSC_RESET (1 << 4) // Port ResetPORTSC_PR
Section titled “PORTSC_PR”#define PORTSC_PR (1 << 4) // Port ResetPORTSC_PLSE
Section titled “PORTSC_PLSE”#define PORTSC_PLSE (1 << 5) // Port Link State EnablePORTSC_PRES
Section titled “PORTSC_PRES”#define PORTSC_PRES (1 << 6) // Port ResumePORTSC_PP
Section titled “PORTSC_PP”#define PORTSC_PP (1 << 9) // Port PowerPORTSC_SPEED_MASK
Section titled “PORTSC_SPEED_MASK”#define PORTSC_SPEED_MASK (0xF << 10) // Bits 10–13: Port SpeedPORTSC_SPEED_SHIFT
Section titled “PORTSC_SPEED_SHIFT”#define PORTSC_SPEED_SHIFT 10PORTSC_PLS_SHIFT
Section titled “PORTSC_PLS_SHIFT”#define PORTSC_PLS_SHIFT 5PORTSC_PLS_MASK
Section titled “PORTSC_PLS_MASK”#define PORTSC_PLS_MASK (0xF << 5)PORTSC_LWS
Section titled “PORTSC_LWS”#define PORTSC_LWS (1 << 16) // Link Write StrobePORTSC_CSC
Section titled “PORTSC_CSC”#define PORTSC_CSC (1 << 17) // Connect Status ChangePORTSC_PEC
Section titled “PORTSC_PEC”#define PORTSC_PEC (1 << 18) // Port Enable/Disable ChangePORTSC_WRC
Section titled “PORTSC_WRC”#define PORTSC_WRC (1 << 19) // Warm Port Reset ChangePORTSC_OCC
Section titled “PORTSC_OCC”#define PORTSC_OCC (1 << 20) // Over-current ChangePORTSC_PRC
Section titled “PORTSC_PRC”#define PORTSC_PRC (1 << 21) // Port Reset ChangePORTSC_PLC
Section titled “PORTSC_PLC”#define PORTSC_PLC (1 << 22) // Port Link State ChangePORTSC_CEC
Section titled “PORTSC_CEC”#define PORTSC_CEC (1 << 23) // Port Config Error ChangePORTSC_PLS_POLLING
Section titled “PORTSC_PLS_POLLING”#define PORTSC_PLS_POLLING 7PORTSC_PLS_U0
Section titled “PORTSC_PLS_U0”#define PORTSC_PLS_U0 0PORTSC_PLS_U2
Section titled “PORTSC_PLS_U2”#define PORTSC_PLS_U2 2PORTSC_PLS_U3
Section titled “PORTSC_PLS_U3”#define PORTSC_PLS_U3 3PORTSC_PLS_RXDETECT
Section titled “PORTSC_PLS_RXDETECT”#define PORTSC_PLS_RXDETECT 5PORTSC_IND
Section titled “PORTSC_IND”#define PORTSC_IND (1 << 24) // Port Indicator ControlPORTSC_LWS_BIT
Section titled “PORTSC_LWS_BIT”#define PORTSC_LWS_BIT (1 << 16) // Link Write StrobePORTSC_DR
Section titled “PORTSC_DR”#define PORTSC_DR (1 << 30) // Device RemovablePORTSC_WPR
Section titled “PORTSC_WPR”#define PORTSC_WPR (1u << 31) // Warm Port ResetPORT_SPEED_FULL
Section titled “PORT_SPEED_FULL”#define PORT_SPEED_FULL 1 // USB 1.1 Full SpeedPORT_SPEED_LOW
Section titled “PORT_SPEED_LOW”#define PORT_SPEED_LOW 2 // USB 1.1 Low SpeedPORT_SPEED_HIGH
Section titled “PORT_SPEED_HIGH”#define PORT_SPEED_HIGH 3 // USB 2.0 High SpeedPORT_SPEED_SUPER
Section titled “PORT_SPEED_SUPER”#define PORT_SPEED_SUPER 4 // USB 3.0 SuperSpeedPORT_SPEED_SUPER_PLUS
Section titled “PORT_SPEED_SUPER_PLUS”#define PORT_SPEED_SUPER_PLUS 5 // USB 3.1 Gen2 (SuperSpeed+)CC_SUCCESS
Section titled “CC_SUCCESS”#define CC_SUCCESS 1CC_DATA_BUFFER_ERROR
Section titled “CC_DATA_BUFFER_ERROR”#define CC_DATA_BUFFER_ERROR 2CC_BABBLE_DETECTED
Section titled “CC_BABBLE_DETECTED”#define CC_BABBLE_DETECTED 3CC_USB_TRANSACTION_ERROR
Section titled “CC_USB_TRANSACTION_ERROR”#define CC_USB_TRANSACTION_ERROR 4CC_TRB_ERROR
Section titled “CC_TRB_ERROR”#define CC_TRB_ERROR 5CC_STALL_ERROR
Section titled “CC_STALL_ERROR”#define CC_STALL_ERROR 6CC_RESOURCE_ERROR
Section titled “CC_RESOURCE_ERROR”#define CC_RESOURCE_ERROR 7CC_BANDWIDTH_ERROR
Section titled “CC_BANDWIDTH_ERROR”#define CC_BANDWIDTH_ERROR 8CC_NO_SLOTS_AVAILABLE
Section titled “CC_NO_SLOTS_AVAILABLE”#define CC_NO_SLOTS_AVAILABLE 9CC_INVALID_STREAM_TYPE
Section titled “CC_INVALID_STREAM_TYPE”#define CC_INVALID_STREAM_TYPE 10CC_SLOT_NOT_ENABLED_ERROR
Section titled “CC_SLOT_NOT_ENABLED_ERROR”#define CC_SLOT_NOT_ENABLED_ERROR 11CC_ENDPOINT_NOT_ENABLED
Section titled “CC_ENDPOINT_NOT_ENABLED”#define CC_ENDPOINT_NOT_ENABLED 12CC_SHORT_PACKET
Section titled “CC_SHORT_PACKET”#define CC_SHORT_PACKET 13CC_RING_UNDERRUN
Section titled “CC_RING_UNDERRUN”#define CC_RING_UNDERRUN 14CC_RING_OVERRUN
Section titled “CC_RING_OVERRUN”#define CC_RING_OVERRUN 15CC_VF_EVENT_RING_FULL_ERROR
Section titled “CC_VF_EVENT_RING_FULL_ERROR”#define CC_VF_EVENT_RING_FULL_ERROR 16CC_PARAMETER_ERROR
Section titled “CC_PARAMETER_ERROR”#define CC_PARAMETER_ERROR 17CC_BANDWIDTH_OVERRUN_ERROR
Section titled “CC_BANDWIDTH_OVERRUN_ERROR”#define CC_BANDWIDTH_OVERRUN_ERROR 18CC_CONTEXT_STATE_ERROR
Section titled “CC_CONTEXT_STATE_ERROR”#define CC_CONTEXT_STATE_ERROR 19CC_NO_PING_RESPONSE_ERROR
Section titled “CC_NO_PING_RESPONSE_ERROR”#define CC_NO_PING_RESPONSE_ERROR 20CC_EVENT_RING_FULL
Section titled “CC_EVENT_RING_FULL”#define CC_EVENT_RING_FULL 21CC_INCOMPATIBLE_DEVICE
Section titled “CC_INCOMPATIBLE_DEVICE”#define CC_INCOMPATIBLE_DEVICE 22CC_MISSED_SERVICE
Section titled “CC_MISSED_SERVICE”#define CC_MISSED_SERVICE 23CC_COMMAND_RING_STOPPED
Section titled “CC_COMMAND_RING_STOPPED”#define CC_COMMAND_RING_STOPPED 24CC_COMMAND_ABORTED
Section titled “CC_COMMAND_ABORTED”#define CC_COMMAND_ABORTED 25CC_STOPPED
Section titled “CC_STOPPED”#define CC_STOPPED 26CC_STOPPED_LEN_INVALID
Section titled “CC_STOPPED_LEN_INVALID”#define CC_STOPPED_LEN_INVALID 27CC_STOPPED_SHORT_PACKET
Section titled “CC_STOPPED_SHORT_PACKET”#define CC_STOPPED_SHORT_PACKET 28CC_MAX_EXIT_LATENCY_TOO_LARGE
Section titled “CC_MAX_EXIT_LATENCY_TOO_LARGE”#define CC_MAX_EXIT_LATENCY_TOO_LARGE 29xhci_log
Section titled “xhci_log”#define xhci_log(log_level, fmt, ...) \
log(LOG_SITE(xhci), LOG_HANDLE(xhci), log_level, fmt, ##__VA_ARGS__)xhci_warn
Section titled “xhci_warn”#define xhci_warn(fmt, ...) xhci_log(LOG_WARN, fmt, ##__VA_ARGS__)xhci_error
Section titled “xhci_error”#define xhci_error(fmt, ...) xhci_log(LOG_ERROR, fmt, ##__VA_ARGS__)xhci_info
Section titled “xhci_info”#define xhci_info(fmt, ...) xhci_log(LOG_INFO, fmt, ##__VA_ARGS__)xhci_debug
Section titled “xhci_debug”#define xhci_debug(fmt, ...) xhci_log(LOG_DEBUG, fmt, ##__VA_ARGS__)xhci_trace
Section titled “xhci_trace”#define xhci_trace(fmt, ...) xhci_log(LOG_TRACE, fmt, ##__VA_ARGS__)XHCI_ERDP_EHB_BIT
Section titled “XHCI_ERDP_EHB_BIT”#define XHCI_ERDP_EHB_BIT (1 << 3)