xHCI

include/drivers/usb/xhci.h View source View on GitHub

Structs

xhci_cap_regs

struct xhci_cap_regs (10 fields)

5.3: XHCI Capability Registers

NOTE

offsets and sizes in kernel/drivers/xhci/layout.c

§ uint8_t cap_length

§ uint8_t reserved

§ uint16_t hci_version

§ uint32_t hcs_params1

§ uint32_t hcs_params2

§ uint32_t hcs_params3

§ uint32_t hcc_params1

§ uint32_t dboff

§ uint32_t rtsoff

§ uint32_t hcc_params2

xhci_port_regs

struct xhci_port_regs (4 fields)

§ uint32_t portsc

Port Status and Control

§ uint32_t portpmsc

Port Power Management Status and Control

§ uint32_t portli

Port Link Info

§ uint32_t portct

Port Configuration Timeout

xhci_usbcmd

struct xhci_usbcmd (1 field)

§ union

§ uint32_t raw

§ struct

§ uint32_t run_stop : 1

§ uint32_t host_controller_reset : 1

§ uint32_t interrupter_enable : 1

§ uint32_t host_system_error_en : 1

§ uint32_t reserved0 : 3

§ uint32_t light_host_controller_reset : 1

§ uint32_t controller_save_state : 1

§ uint32_t controller_restore_state : 1

§ uint32_t enable_wrap_event : 1

§ uint32_t enable_u3_mf_index : 1

§ uint32_t reserved1 : 1

§ uint32_t cem_enable : 1

§ uint32_t extended_tbc_enable : 1

§ uint32_t extended_tbc_trb_status_enable : 1

§ uint32_t vtio_enable : 1

§ uint32_t reserved2 : 15

xhci_slot_ctx

struct xhci_slot_ctx (18 fields)

Page 444

§ uint32_t route_string : 20

Location in USB topology

§ uint32_t speed : 4

Speed of the device

§ uint32_t reserved0 : 1

§ uint32_t mtt : 1

Set to ‘1’ by software if this is a high speed hub that supports multiple TTs

§ uint32_t hub : 1

Set to ‘1’ by software if this is a USB hub, 0 if function

§ uint32_t context_entries : 5

Index of the last valid endpoint context within this structure

§ uint32_t max_exit_latency : 16

In microseconds, worst case time it takes to wake up all links in path to device

§ uint32_t root_hub_port : 8

Root hub port number used to access the USB device

§ uint32_t num_ports : 8

If this is a hub, this is set by software to identify downstream ports supported by the hub

§ uint32_t parent_hub_slot_id : 8

Slot ID of the parent high-speed hub

§ uint32_t parent_port_number : 8

Port number of the parent high-speed hub

§ uint32_t parent_think_time : 2

Think time of the parent high-speed hub

§ uint32_t reserved1 : 4

§ uint32_t interrupter_target : 10

Index of the interrupter to events generated by this slot

§ uint32_t usb_device_address : 8

Address of USB device assigned by xHC

§ uint32_t reserved2 : 19

§ uint32_t slot_state : 5

0 - disabled/enabled, 1 - default, 2 - addressed, 3 - configured, rest reserved

§ uint32_t reserved3[4]

xhci_ep_ctx

struct xhci_ep_ctx (18 fields)

Refer to page 450 of the XHCI specification

§ uint32_t ep_state : 3

The current operational state of the endpoint 0 - Disabled (non-operational) 1 - Running 2 - Halted 3 - Stopped 4 - Error - SW can manipulate the transfer ring 5-7 - Reserved

§ uint32_t reserved1 : 5

§ uint32_t mult : 2

Maximum number of bursts in an interval that this endpoint supports. Zero-based value, 0-3 is 1-4 bursts 0 for all endpoint types except SS Isochronous

§ uint32_t max_pstreams : 5

Maximum Primary streams this endpoint supports. If this is ‘0’, the TR dequeue pointer should point to a transfer ring. If this is > ‘0’ the TR dequeue pointer points to a Primary Stream Context Array.

§ uint32_t lsa : 1

Linear Stream Array, identifies how an ID stream is interpreted ‘1’ disables Secondary Stream Arrays Linear index into Primary Stream Array Valid values are MaxPstreams 1 - 15

§ uint32_t interval : 8

Period between consecutive requests to a USB endpoint, expressed in 125 microsecond increments. Interval of 0 means period of 125us. A value of 1 means a period of 250us, etc.

§ uint32_t max_esit_payload_hi : 8

Max Endpoint Service Time Interval Payload High If LEC is ‘1’ this is the high order 8 bits of the max ESIT payload value. If this is ‘0’, then this is reserved

§ uint32_t reserved2 : 1

§ uint32_t error_count : 2

Two bit down count, identifying the number of consecutive USB-bus errors allowed while executing a TD.

§ uint32_t ep_type : 3

Endpoint type 0 - Not valid 1 - Isochronous Out 2 - Bulk Out 3 - Interrupt Out 4 - Control Bidirectional 5 - Isochronous In 6 - Bulk In 7 - Interrupt In

§ uint32_t reserved3 : 1

§ uint32_t host_initiate_disable : 1

The field affects Stream enabled endpoints allowing the HI stream selection feature to be disabled for the endpoint. Setting to ‘1’ disables the HI stream selection feature. ‘0’ enables normal stream operation

§ uint32_t max_burst_size : 8

Maximum number of consecutive USB transactions per scheduling opportunity. 0-based, 0-15 means 1-16

§ uint32_t max_packet_size : 16

Max packet size in bytes that this endpoint is capable of sending or receiving when configured.

§ union

§ uint64_t dequeue_ptr_raw

§ struct

§ uint32_t dcs : 1

Dequeue cycle state - value of the xHC CCS (Consumer Cycle State) flag for the TRB referenced by the TR Dequeue pointer. ‘0’ if max_pstreams > ‘0’

§ uint32_t reserved4 : 3

§ uint64_t dequeue_ptr : 60

dequeue pointer MUST be aligned to 16 BYTE BOUNDARY

§ uint32_t average_trb_length : 16

Average length of TRBs executed by this endpoint. Must be > ‘0’

§ uint32_t max_esit_payload_lo : 16

Low order 16 bits of max ESIT payload. Represends the total number of bytes this endpoint will transfer during an ESIT

§ uint32_t reserved5[3]

xhci_input_ctrl_ctx

struct xhci_input_ctrl_ctx (7 fields)

Refer to page 461 of the XHCI specification

§ uint32_t drop_flags

Single bitfields to identify which device context data structs should be disabled by command. ‘1’ disables the respective EP CTX.

First two bits reserved

§ uint32_t add_flags

Single bitfields to identify which device CTX data structures should be evaluated or enabled by command. ‘1’ enables the respective CTX

§ uint32_t reserved[5]

§ uint32_t config : 8

If CIC = ‘1’ and CIE = ‘1’, and this input CTX is associated with a Configure Endpoint command, this field contains the value of the Standard Configuration Descriptor bConfiguration field associated with this command. Otherwise, clear to ‘0’

§ uint32_t interface_num : 8

If CIC = ‘1’ and CIE = ‘1’, and this input CTX is associated with a Configure Endpoint Command, and this command was issued due to a SET_INTERFACE request, this contains the Standard Interface Descriptor bInterfaceNumber field associated with the command. Otherwise, clear to ‘0’

§ uint32_t alternate_setting : 8

If CIC = ‘1’ and CIE = ‘1’, and this input CTX is associated with a Configure Endpoint command, and the command was issued due to a SET_INTERFACE request, then this field contains the value of the Standard Interface Descriptor bAlternateSetting field associated with the command. Otherwise, clear to ‘0’.

§ uint32_t reserved1 : 8

xhci_input_ctx

struct xhci_input_ctx (3 fields)

Refer to page 460 of the XHCI Spec

§ struct xhci_input_ctrl_ctx ctrl_ctx

§ struct xhci_slot_ctx slot_ctx

§ struct xhci_ep_ctx ep_ctx[31]

xhci_device_ctx

struct xhci_device_ctx (2 fields)

§ struct xhci_slot_ctx slot_ctx

§ struct xhci_ep_ctx ep_ctx[32]

Endpoint 1–31 (ep0 separate)

xhci_op_regs

struct xhci_op_regs (11 fields)

§ struct xhci_usbcmd usbcmd

§ uint32_t usbsts

§ uint32_t pagesize

§ uint32_t reserved[2]

§ uint32_t dnctrl

§ uint64_t crcr

§ uint32_t reserved2[4]

§ uint64_t dcbaap

§ uint32_t config

§ uint32_t reserved3[241]

§ struct xhci_port_regs regs[]

xhci_trb

struct xhci_trb (3 fields)

§ uint64_t parameter

§ uint32_t status

§ uint32_t control

xhci_ring

struct xhci_ring (7 fields)

§ struct xhci_trb *trbs

Virtual mapped TRB buffer

§ uint64_t phys

Physical address of TRB buffer

§ uint32_t enqueue_index

Next TRB to fill

§ uint32_t dequeue_index

Point where controller sends back things

§ uint8_t cycle

Cycle bit, toggles after ring wrap

§ uint32_t size

Number of TRBs in ring

§ size_t outgoing

xhci_erst_entry

struct xhci_erst_entry (3 fields)

§ uint64_t ring_segment_base

§ uint32_t ring_segment_size

§ uint32_t reserved

xhci_interrupter_regs

struct xhci_interrupter_regs (6 fields)

Page 424

§ uint32_t iman

Interrupt management

§ uint32_t imod

Interrupt moderation

§ uint32_t erstsz

Event Ring Segment Table Size

§ uint32_t reserved

§ uint64_t erstba

Event Ring Segment Table Base Address

§ uint64_t erdp

xhci_dcbaa

struct xhci_dcbaa (1 field)

Device context base address array - check page 441

§ uint64_t ptrs[256]

xhci_ext_cap

struct xhci_ext_cap (3 fields)

§ uint8_t cap_id

§ uint8_t next

§ uint16_t cap_specific

xhci_slot

struct xhci_slot (7 fields)

§ atomic(enum xhci_slot_state) state

§ struct xhci_device *dev

§ struct xhci_ring *ep_rings[32]

§ uint8_t slot_id

Just so everyone knows what slot we are

§ refcount_t refcount

As soon as this drops to zero we clear the ep_rings

§ struct xhci_port *port

§ struct usb_device *udev

xhci_port

struct xhci_port (8 fields)

§ struct spinlock update_lock

Raw spinlock to protect against concurrent updating

§ uint8_t port_id

§ struct xhci_slot *slot

§ uint8_t speed

§ bool usb3

§ uint64_t generation

§ enum xhci_port_state state

§ struct xhci_device *dev

xhci_device

struct xhci_device (23 fields)

§ irq_t irq

What IRQ line have we routed to this?

§ struct pci_device *pci

§ struct xhci_input_ctx *input_ctx

§ struct xhci_cap_regs cc_mem_io *cap_regs

Capability registers

§ struct xhci_op_regs cc_mem_io *op_regs

Operational registers

§ struct xhci_interrupter_regs cc_mem_io *intr_regs

Interrupter regs

§ struct xhci_dcbaa *dcbaa

§ struct xhci_ring *event_ring

§ struct xhci_ring *cmd_ring

§ struct xhci_erst_entry *erst

§ struct xhci_port_regs cc_mem_io *port_regs

§ uint64_t ports

§ struct xhci_slot slots[XHCI_SLOT_COUNT]

§ struct xhci_port port_info[XHCI_PORT_COUNT]

§ struct list_head requests[XHCI_REQ_LIST_MAX]

§ size_t num_devices

§ struct list_head devices

§ struct spinlock lock

§ struct semaphore sem

§ struct semaphore port_disconnect

§ struct semaphore port_connect

§ struct usb_controller *controller

§ atomic_bool worker_waiting

xhci_command

struct xhci_command (7 fields)

§ struct xhci_ring *ring

what ring?

§ struct xhci_slot *slot

§ uint32_t ep_id

§ size_t num_trbs

§ void (*emit)(struct xhci_command *cmd, struct xhci_ring *ring)

§ struct xhci_request *request

associated request

§ void *private

xhci_request

struct xhci_request (17 fields)

§ struct event event

§ enum xhci_request_command_type type

Tied back to the USB request

§ enum xhci_request_list list_owner

§ struct usb_request *urb

§ struct xhci_command *command

§ struct xhci_trb *last_trb

§ uint64_t trb_phys

§ uint8_t port

What port is this for? Used to match requests on disconnect

§ volatile uint8_t completion_code

the raw completion code for this request

§ volatile uint64_t return_parameter

§ volatile uint32_t return_status

§ volatile uint32_t return_control

§ uint64_t generation

§ volatile enum xhci_request_status status

§ struct list_node list

§ void (*callback)(struct xhci_device *, struct xhci_request *)

§ void *private

xhci_return

struct xhci_return (2 fields)

§ uint32_t control

§ uint32_t status

Enums

xhci_slot_state

enum xhci_slot_state (4 variants)

§ XHCI_SLOT_STATE_UNDEF

§ XHCI_SLOT_STATE_ENABLED

§ XHCI_SLOT_STATE_DISCONNECTING

§ XHCI_SLOT_STATE_DISCONNECTED

xhci_port_state

enum xhci_port_state (5 variants)

§ XHCI_PORT_STATE_UNDEF

§ XHCI_PORT_STATE_CONNECTING

§ XHCI_PORT_STATE_CONNECTED

§ XHCI_PORT_STATE_DISCONNECTING

§ XHCI_PORT_STATE_DISCONNECTED

xhci_request_status

enum xhci_request_status (5 variants)

§ XHCI_REQUEST_SENDING

The first 3 statuses indicate list state.

OUTGOING requests have a TRB, and have rang the doorbell.

WAITING requests cannot be currently satisfied because the command ring is full.

PROCESSED requests have been handled by the ISR with a success state. Technically they run in the worker thread but the status is set from ISR.

DISCONNECT requests occur when a port is disconnected and the request no longer goes anywhere (because the port is gone)

§ XHCI_REQUEST_OK

§ XHCI_REQUEST_CANCELLED

§ XHCI_REQUEST_DISCONNECT

§ XHCI_REQUEST_ERR

xhci_request_list

enum xhci_request_list (5 variants)

§ XHCI_REQ_LIST_NONE

§ XHCI_REQ_LIST_OUTGOING

§ XHCI_REQ_LIST_WAITING

§ XHCI_REQ_LIST_PROCESSED

§ XHCI_REQ_LIST_MAX

xhci_request_command_type

enum xhci_request_command_type (15 variants)

Abstract command types, not 1:1

§ XHCI_CMD_TYPE_NONE

§ XHCI_CMD_TYPE_ENABLE_SLOT

§ XHCI_CMD_TYPE_DISABLE_SLOT

§ XHCI_CMD_TYPE_ADDRESS_DEVICE

§ XHCI_CMD_TYPE_CONFIGURE_ENDPOINT

§ XHCI_CMD_TYPE_EVALUATE_CONTEXT

§ XHCI_CMD_TYPE_RESET_ENDPOINT

§ XHCI_CMD_TYPE_STOP_ENDPOINT

§ XHCI_CMD_TYPE_SET_TR_DEQUEUE_POINTER

§ XHCI_CMD_TYPE_RESET_DEVICE

§ XHCI_CMD_TYPE_FORCE_EVENT

§ XHCI_CMD_TYPE_INTERRUPT_TRANSFER

§ XHCI_CMD_TYPE_CONTROL_TRANSFER

§ XHCI_CMD_TYPE_NO_OP

§ XHCI_CMD_TYPE_NORMAL

‘misc.‘

Functions

xhci_slot_state_str

const char * xhci_slot_state_str(enum xhci_slot_state s)

xhci_port_state_str

const char * xhci_port_state_str(enum xhci_port_state s)

xhci_request_command_type_str

const char * xhci_request_command_type_str(enum xhci_request_command_type t)

xhci_init

void xhci_init(
    uint8_t bus,
    uint8_t slot,
    uint8_t func,
    struct pci_device *dev
)

Macros

XHCI_DEVICE_TIMEOUT

#define XHCI_DEVICE_TIMEOUT 1000

TRB_RING_SIZE

#define TRB_RING_SIZE 256

XHCI_PORT_COUNT

#define XHCI_PORT_COUNT 64

XHCI_SLOT_COUNT

#define XHCI_SLOT_COUNT 255

XHCI_INPUT_CTX_ADD_FLAGS

#define XHCI_INPUT_CTX_ADD_FLAGS (BIT(0) | BIT(1))

XHCI_SETUP_TRANSFER_TYPE_NONE

#define XHCI_SETUP_TRANSFER_TYPE_NONE 0

XHCI_SETUP_TRANSFER_TYPE_OUT

#define XHCI_SETUP_TRANSFER_TYPE_OUT 2

XHCI_SETUP_TRANSFER_TYPE_IN

#define XHCI_SETUP_TRANSFER_TYPE_IN 3

XHCI_USBSTS_HCH

#define XHCI_USBSTS_HCH 1

HC halted

XHCI_USBSTS_HSE

#define XHCI_USBSTS_HSE BIT(2)

host system error

XHCI_USBSTS_EI

#define XHCI_USBSTS_EI BIT(3)

event interrupt

XHCI_USBSTS_PCD

#define XHCI_USBSTS_PCD BIT(4)

port change detect

XHCI_IMAN_MASK

#define XHCI_IMAN_MASK 0x2

XHCI_IMAN_INT_PENDING

#define XHCI_IMAN_INT_PENDING 0x1

XHCI_IMAN_INT_ENABLE

#define XHCI_IMAN_INT_ENABLE 0x2

XHCI_ENDPOINT_TYPE_INVAL

#define XHCI_ENDPOINT_TYPE_INVAL 0

XHCI_ENDPOINT_TYPE_ISOCH_OUT

#define XHCI_ENDPOINT_TYPE_ISOCH_OUT 1

XHCI_ENDPOINT_TYPE_BULK_OUT

#define XHCI_ENDPOINT_TYPE_BULK_OUT 2

XHCI_ENDPOINT_TYPE_INTERRUPT_OUT

#define XHCI_ENDPOINT_TYPE_INTERRUPT_OUT 3

XHCI_ENDPOINT_TYPE_CONTROL_BI

#define XHCI_ENDPOINT_TYPE_CONTROL_BI 4

XHCI_ENDPOINT_TYPE_ISOCH_IN

#define XHCI_ENDPOINT_TYPE_ISOCH_IN 5

XHCI_ENDPOINT_TYPE_BULK_IN

#define XHCI_ENDPOINT_TYPE_BULK_IN 6

XHCI_ENDPOINT_TYPE_INTERRUPT_IN

#define XHCI_ENDPOINT_TYPE_INTERRUPT_IN 7

XHCI_EXT_CAP_ID_LEGACY_SUPPORT

#define XHCI_EXT_CAP_ID_LEGACY_SUPPORT 1

NOTE

In scatter gathers, the first TRD must NOT point to a page-aligned boundary. Following TRDs must point to page-aligned boundaries.

XHCI_EXT_CAP_ID_USB

#define XHCI_EXT_CAP_ID_USB 2

TRB_TYPE_RESERVED

#define TRB_TYPE_RESERVED 0x00

TRB Types (bits 10–15 in control word)

TRB_TYPE_NORMAL

#define TRB_TYPE_NORMAL 0x01

TRB_TYPE_SETUP_STAGE

#define TRB_TYPE_SETUP_STAGE 0x02

TRB_TYPE_DATA_STAGE

#define TRB_TYPE_DATA_STAGE 0x03

TRB_TYPE_STATUS_STAGE

#define TRB_TYPE_STATUS_STAGE 0x04

TRB_TYPE_ISOCH

#define TRB_TYPE_ISOCH 0x05

TRB_TYPE_LINK

#define TRB_TYPE_LINK 0x06

TRB_TYPE_EVENT_DATA

#define TRB_TYPE_EVENT_DATA 0x07

TRB_TYPE_NO_OP

#define TRB_TYPE_NO_OP 0x08

Command TRBs

TRB_TYPE_NO_OP_COMMAND

#define TRB_TYPE_NO_OP_COMMAND 0x8

TRB_TYPE_ENABLE_SLOT

#define TRB_TYPE_ENABLE_SLOT 0x09

TRB_TYPE_DISABLE_SLOT

#define TRB_TYPE_DISABLE_SLOT 0x0A

TRB_TYPE_ADDRESS_DEVICE

#define TRB_TYPE_ADDRESS_DEVICE 0x0B

TRB_TYPE_CONFIGURE_ENDPOINT

#define TRB_TYPE_CONFIGURE_ENDPOINT 0x0C

TRB_TYPE_EVALUATE_CONTEXT

#define TRB_TYPE_EVALUATE_CONTEXT 0x0D

TRB_TYPE_RESET_ENDPOINT

#define TRB_TYPE_RESET_ENDPOINT 0x0E

TRB_TYPE_STOP_ENDPOINT

#define TRB_TYPE_STOP_ENDPOINT 0x0F

TRB_TYPE_SET_TR_DEQUEUE_POINTER

#define TRB_TYPE_SET_TR_DEQUEUE_POINTER 0x10

TRB_TYPE_RESET_DEVICE

#define TRB_TYPE_RESET_DEVICE 0x11

TRB_TYPE_FORCE_EVENT

#define TRB_TYPE_FORCE_EVENT 0x12

TRB_TYPE_NEGOTIATE_BW

#define TRB_TYPE_NEGOTIATE_BW 0x13

TRB_TYPE_SET_LATENCY_TOLERANCE

#define TRB_TYPE_SET_LATENCY_TOLERANCE 0x14

TRB_TYPE_GET_PORT_BANDWIDTH

#define TRB_TYPE_GET_PORT_BANDWIDTH 0x15

TRB_TYPE_FORCE_HEADER

#define TRB_TYPE_FORCE_HEADER 0x16

TRB_TYPE_NO_OP_2_COMMAND

#define TRB_TYPE_NO_OP_2_COMMAND 0x17

Event TRBs

TRB_TYPE_TRANSFER_EVENT

#define TRB_TYPE_TRANSFER_EVENT 0x20

TRB_TYPE_COMMAND_COMPLETION

#define TRB_TYPE_COMMAND_COMPLETION 0x21

TRB_TYPE_PORT_STATUS_CHANGE

#define TRB_TYPE_PORT_STATUS_CHANGE 0x22

TRB_TYPE_BANDWIDTH_REQUEST

#define TRB_TYPE_BANDWIDTH_REQUEST 0x23

TRB_TYPE_DOORBELL_EVENT

#define TRB_TYPE_DOORBELL_EVENT 0x24

TRB_TYPE_HOST_CONTROLLER_EVENT

#define TRB_TYPE_HOST_CONTROLLER_EVENT 0x25

TRB_TYPE_DEVICE_NOTIFICATION

#define TRB_TYPE_DEVICE_NOTIFICATION 0x26

TRB_TYPE_MFINDEX_WRAP

#define TRB_TYPE_MFINDEX_WRAP 0x27

TRB_FIELD

#define TRB_FIELD(val, lo, hi)

Expansion

#define TRB_FIELD(val, lo, hi) BIT_RANGE(val, lo, hi)

TRB_TYPE

#define TRB_TYPE(ctrl)

Expansion

#define TRB_TYPE(ctrl) TRB_FIELD(ctrl, 10, 15)

TRB_SLOT

#define TRB_SLOT(ctrl)

Expansion

#define TRB_SLOT(ctrl) TRB_FIELD(ctrl, 24, 31)

TRB_EP

#define TRB_EP(ctrl)

Expansion

#define TRB_EP(ctrl) TRB_FIELD(ctrl, 16, 23)

TRB_CC

#define TRB_CC(status)

Expansion

#define TRB_CC(status) TRB_FIELD(status, 24, 31)

TRB_PORT

#define TRB_PORT(parameter)

Expansion

#define TRB_PORT(parameter) TRB_FIELD(parameter, 24, 31)

TRB_SET_TYPE

#define TRB_SET_TYPE(val)

Expansion

#define TRB_SET_TYPE(val) (((val) & 0x3F) << 10)

TRB_SET_CYCLE

#define TRB_SET_CYCLE(val)

Expansion

#define TRB_SET_CYCLE(val) (((val) & 1))

TRB_SET_INTERRUPTER_TARGET

#define TRB_SET_INTERRUPTER_TARGET(target)

Expansion

#define TRB_SET_INTERRUPTER_TARGET(target) (((uint32_t) (target) & 0x3FF) << 22)

TRB_CYCLE_BIT

#define TRB_CYCLE_BIT BIT(0)

TRB_ENT_BIT

#define TRB_ENT_BIT BIT(1)

Evaluate Next TRB

TRB_ISP_BIT

#define TRB_ISP_BIT BIT(2)

Interrupt on Short Packet

TRB_NS_BIT

#define TRB_NS_BIT BIT(3)

No Snoop

TRB_CH_BIT

#define TRB_CH_BIT BIT(4)

Chain

TRB_IOC_BIT

#define TRB_IOC_BIT BIT(5)

Interrupt On Completion

TRB_IDT_BIT

#define TRB_IDT_BIT BIT(6)

Immediate Data

TRB_BEI_BIT

#define TRB_BEI_BIT BIT(9)

Block Event Interrupt (ISO)

TRB_TOGGLE_CYCLE_BIT

#define TRB_TOGGLE_CYCLE_BIT BIT(1)

TRB_TYPE_SHIFT

#define TRB_TYPE_SHIFT 10

TRB_SET_SLOT_ID

#define TRB_SET_SLOT_ID(id)

Expansion

#define TRB_SET_SLOT_ID(id) (((id) & 0xFF) << 24)

PORTSC_CCS

#define PORTSC_CCS BIT(0)

Bit definitions for XHCI PORTSC register

Current Connect Status

PORTSC_PED

#define PORTSC_PED BIT(1)

Port Enabled/Disabled

PORTSC_OCA

#define PORTSC_OCA BIT(3)

Over-Current Active

PORTSC_RESET

#define PORTSC_RESET BIT(4)

Port Reset

PORTSC_PR

#define PORTSC_PR BIT(4)

Port Reset

PORTSC_PLSE

#define PORTSC_PLSE BIT(5)

Port Link State Enable

PORTSC_PRES

#define PORTSC_PRES BIT(6)

Port Resume

PORTSC_PP

#define PORTSC_PP BIT(9)

Port Power

PORTSC_SPEED_MASK

#define PORTSC_SPEED_MASK (0xF << 10)

Bits 10–13: Port Speed

PORTSC_SPEED_SHIFT

#define PORTSC_SPEED_SHIFT 10

PORTSC_PLS_SHIFT

#define PORTSC_PLS_SHIFT 5

PORTSC_PLS_MASK

#define PORTSC_PLS_MASK (0xF << 5)

PORTSC_LWS

#define PORTSC_LWS BIT(16)

Link Write Strobe

PORTSC_CSC

#define PORTSC_CSC BIT(17)

Connect Status Change

PORTSC_PEC

#define PORTSC_PEC BIT(18)

Port Enable/Disable Change

PORTSC_WRC

#define PORTSC_WRC BIT(19)

Warm Port Reset Change

PORTSC_OCC

#define PORTSC_OCC BIT(20)

Over-current Change

PORTSC_PRC

#define PORTSC_PRC BIT(21)

Port Reset Change

PORTSC_PLC

#define PORTSC_PLC BIT(22)

Port Link State Change

PORTSC_CEC

#define PORTSC_CEC BIT(23)

Port Config Error Change

PORTSC_PLS_POLLING

#define PORTSC_PLS_POLLING 7

PORTSC_PLS_U0

#define PORTSC_PLS_U0 0

PORTSC_PLS_U2

#define PORTSC_PLS_U2 2

PORTSC_PLS_U3

#define PORTSC_PLS_U3 3

PORTSC_PLS_RXDETECT

#define PORTSC_PLS_RXDETECT 5

PORTSC_IND

#define PORTSC_IND BIT(24)

Port Indicator Control

PORTSC_LWS_BIT

#define PORTSC_LWS_BIT BIT(16)

Link Write Strobe

PORTSC_DR

#define PORTSC_DR BIT(30)

Device Removable

PORTSC_WPR

#define PORTSC_WPR BIT(31)

Warm Port Reset

PORT_SPEED_FULL

#define PORT_SPEED_FULL 1

USB 1.1 Full Speed

PORT_SPEED_LOW

#define PORT_SPEED_LOW 2

USB 1.1 Low Speed

PORT_SPEED_HIGH

#define PORT_SPEED_HIGH 3

USB 2.0 High Speed

PORT_SPEED_SUPER

#define PORT_SPEED_SUPER 4

USB 3.0 SuperSpeed

PORT_SPEED_SUPER_PLUS

#define PORT_SPEED_SUPER_PLUS 5

USB 3.1 Gen2 (SuperSpeed+)

CC_SUCCESS

#define CC_SUCCESS 1

CC_DATA_BUFFER_ERROR

#define CC_DATA_BUFFER_ERROR 2

CC_BABBLE_DETECTED

#define CC_BABBLE_DETECTED 3

CC_USB_TRANSACTION_ERROR

#define CC_USB_TRANSACTION_ERROR 4

CC_TRB_ERROR

#define CC_TRB_ERROR 5

CC_STALL_ERROR

#define CC_STALL_ERROR 6

CC_RESOURCE_ERROR

#define CC_RESOURCE_ERROR 7

CC_BANDWIDTH_ERROR

#define CC_BANDWIDTH_ERROR 8

CC_NO_SLOTS_AVAILABLE

#define CC_NO_SLOTS_AVAILABLE 9

CC_INVALID_STREAM_TYPE

#define CC_INVALID_STREAM_TYPE 10

CC_SLOT_NOT_ENABLED_ERROR

#define CC_SLOT_NOT_ENABLED_ERROR 11

CC_ENDPOINT_NOT_ENABLED

#define CC_ENDPOINT_NOT_ENABLED 12

CC_SHORT_PACKET

#define CC_SHORT_PACKET 13

CC_RING_UNDERRUN

#define CC_RING_UNDERRUN 14

CC_RING_OVERRUN

#define CC_RING_OVERRUN 15

CC_VF_EVENT_RING_FULL_ERROR

#define CC_VF_EVENT_RING_FULL_ERROR 16

CC_PARAMETER_ERROR

#define CC_PARAMETER_ERROR 17

CC_BANDWIDTH_OVERRUN_ERROR

#define CC_BANDWIDTH_OVERRUN_ERROR 18

CC_CONTEXT_STATE_ERROR

#define CC_CONTEXT_STATE_ERROR 19

CC_NO_PING_RESPONSE_ERROR

#define CC_NO_PING_RESPONSE_ERROR 20

CC_EVENT_RING_FULL

#define CC_EVENT_RING_FULL 21

CC_INCOMPATIBLE_DEVICE

#define CC_INCOMPATIBLE_DEVICE 22

CC_MISSED_SERVICE

#define CC_MISSED_SERVICE 23

CC_COMMAND_RING_STOPPED

#define CC_COMMAND_RING_STOPPED 24

CC_COMMAND_ABORTED

#define CC_COMMAND_ABORTED 25

CC_STOPPED

#define CC_STOPPED 26

CC_STOPPED_LEN_INVALID

#define CC_STOPPED_LEN_INVALID 27

CC_STOPPED_SHORT_PACKET

#define CC_STOPPED_SHORT_PACKET 28

CC_MAX_EXIT_LATENCY_TOO_LARGE

#define CC_MAX_EXIT_LATENCY_TOO_LARGE 29

xhci_log

#define xhci_log(log_level, fmt, ...)

Expansion

#define xhci_log(log_level, fmt, ...) \
    log(LOG_SITE(xhci), LOG_HANDLE(xhci), log_level, fmt, ##__VA_ARGS__)

xhci_warn

#define xhci_warn(fmt, ...)

Expansion

#define xhci_warn(fmt, ...) xhci_log(LOG_WARN, fmt, ##__VA_ARGS__)

xhci_error

#define xhci_error(fmt, ...)

Expansion

#define xhci_error(fmt, ...) xhci_log(LOG_ERROR, fmt, ##__VA_ARGS__)

xhci_info

#define xhci_info(fmt, ...)

Expansion

#define xhci_info(fmt, ...) xhci_log(LOG_INFO, fmt, ##__VA_ARGS__)

xhci_debug

#define xhci_debug(fmt, ...)

Expansion

#define xhci_debug(fmt, ...) xhci_log(LOG_DEBUG, fmt, ##__VA_ARGS__)

xhci_trace

#define xhci_trace(fmt, ...)

Expansion

#define xhci_trace(fmt, ...) xhci_log(LOG_TRACE, fmt, ##__VA_ARGS__)

XHCI_ERDP_EHB_BIT

#define XHCI_ERDP_EHB_BIT BIT(3)