1/* @title: xHCI */
2#pragma once
3#include <compiler/core.h>
4#include <log.h>
5#include <math/bit.h>
6#include <stdbool.h>
7#include <stdint.h>
8#include <structures/list.h>
9#include <structures/locked_list.h>
10#include <sync/event.h>
11#include <sync/semaphore.h>
12#include <thread/workqueue.h>
13#include <types/types.h>
14struct usb_controller;
15struct usb_packet;
16struct xhci_request;
17struct usb_endpoint;
18struct pci_device;
19
20#define XHCI_DEVICE_TIMEOUT 1000
21#define TRB_RING_SIZE 256
22#define XHCI_PORT_COUNT 64
23#define XHCI_SLOT_COUNT 255
24
25#define XHCI_INPUT_CTX_ADD_FLAGS (BIT(0) | BIT(1))
26
27#define XHCI_SETUP_TRANSFER_TYPE_NONE 0
28#define XHCI_SETUP_TRANSFER_TYPE_OUT 2
29#define XHCI_SETUP_TRANSFER_TYPE_IN 3
30
31#define XHCI_USBSTS_HCH 1 /* HC halted */
32#define XHCI_USBSTS_HSE BIT(2) /* host system error */
33#define XHCI_USBSTS_EI BIT(3) /* event interrupt */
34#define XHCI_USBSTS_PCD BIT(4) /* port change detect */
35#define XHCI_IMAN_MASK 0x2
36#define XHCI_IMAN_INT_PENDING 0x1
37#define XHCI_IMAN_INT_ENABLE 0x2
38
39#define XHCI_ENDPOINT_TYPE_INVAL 0
40#define XHCI_ENDPOINT_TYPE_ISOCH_OUT 1
41#define XHCI_ENDPOINT_TYPE_BULK_OUT 2
42#define XHCI_ENDPOINT_TYPE_INTERRUPT_OUT 3
43#define XHCI_ENDPOINT_TYPE_CONTROL_BI 4
44#define XHCI_ENDPOINT_TYPE_ISOCH_IN 5
45#define XHCI_ENDPOINT_TYPE_BULK_IN 6
46#define XHCI_ENDPOINT_TYPE_INTERRUPT_IN 7
47
48// NOTE: In scatter gathers, the first TRD must NOT point to a page-aligned
49// boundary. Following TRDs must point to page-aligned boundaries.
50
51#define XHCI_EXT_CAP_ID_LEGACY_SUPPORT 1
52#define XHCI_EXT_CAP_ID_USB 2
53
54// TRB Types (bits 10–15 in control word)
55#define TRB_TYPE_RESERVED 0x00
56#define TRB_TYPE_NORMAL 0x01
57#define TRB_TYPE_SETUP_STAGE 0x02
58#define TRB_TYPE_DATA_STAGE 0x03
59#define TRB_TYPE_STATUS_STAGE 0x04
60#define TRB_TYPE_ISOCH 0x05
61#define TRB_TYPE_LINK 0x06
62#define TRB_TYPE_EVENT_DATA 0x07
63#define TRB_TYPE_NO_OP 0x08
64
65// Command TRBs
66#define TRB_TYPE_NO_OP_COMMAND 0x8
67#define TRB_TYPE_ENABLE_SLOT 0x09
68#define TRB_TYPE_DISABLE_SLOT 0x0A
69#define TRB_TYPE_ADDRESS_DEVICE 0x0B
70#define TRB_TYPE_CONFIGURE_ENDPOINT 0x0C
71#define TRB_TYPE_EVALUATE_CONTEXT 0x0D
72#define TRB_TYPE_RESET_ENDPOINT 0x0E
73#define TRB_TYPE_STOP_ENDPOINT 0x0F
74#define TRB_TYPE_SET_TR_DEQUEUE_POINTER 0x10
75#define TRB_TYPE_RESET_DEVICE 0x11
76#define TRB_TYPE_FORCE_EVENT 0x12
77#define TRB_TYPE_NEGOTIATE_BW 0x13
78#define TRB_TYPE_SET_LATENCY_TOLERANCE 0x14
79#define TRB_TYPE_GET_PORT_BANDWIDTH 0x15
80#define TRB_TYPE_FORCE_HEADER 0x16
81#define TRB_TYPE_NO_OP_2_COMMAND 0x17
82
83// Event TRBs
84#define TRB_TYPE_TRANSFER_EVENT 0x20
85#define TRB_TYPE_COMMAND_COMPLETION 0x21
86#define TRB_TYPE_PORT_STATUS_CHANGE 0x22
87#define TRB_TYPE_BANDWIDTH_REQUEST 0x23
88#define TRB_TYPE_DOORBELL_EVENT 0x24
89#define TRB_TYPE_HOST_CONTROLLER_EVENT 0x25
90#define TRB_TYPE_DEVICE_NOTIFICATION 0x26
91#define TRB_TYPE_MFINDEX_WRAP 0x27
92
93#define TRB_FIELD(val, lo, hi) BIT_RANGE(val, lo, hi)
94
95#define TRB_TYPE(ctrl) TRB_FIELD(ctrl, 10, 15)
96#define TRB_SLOT(ctrl) TRB_FIELD(ctrl, 24, 31)
97#define TRB_EP(ctrl) TRB_FIELD(ctrl, 16, 23)
98
99#define TRB_CC(status) TRB_FIELD(status, 24, 31)
100#define TRB_PORT(parameter) TRB_FIELD(parameter, 24, 31)
101
102#define TRB_SET_TYPE(val) (((val) & 0x3F) << 10)
103#define TRB_SET_CYCLE(val) (((val) & 1))
104#define TRB_SET_INTERRUPTER_TARGET(target) (((uint32_t) (target) & 0x3FF) << 22)
105
106#define TRB_CYCLE_BIT BIT(0)
107#define TRB_ENT_BIT BIT(1) // Evaluate Next TRB
108#define TRB_ISP_BIT BIT(2) // Interrupt on Short Packet
109#define TRB_NS_BIT BIT(3) // No Snoop
110#define TRB_CH_BIT BIT(4) // Chain
111#define TRB_IOC_BIT BIT(5) // Interrupt On Completion
112#define TRB_IDT_BIT BIT(6) // Immediate Data
113#define TRB_BEI_BIT BIT(9) // Block Event Interrupt (ISO)
114#define TRB_TOGGLE_CYCLE_BIT BIT(1)
115#define TRB_TYPE_SHIFT 10
116
117#define TRB_SET_SLOT_ID(id) (((id) & 0xFF) << 24)
118
119// Bit definitions for XHCI PORTSC register
120#define PORTSC_CCS BIT(0) // Current Connect Status
121#define PORTSC_PED BIT(1) // Port Enabled/Disabled
122#define PORTSC_OCA BIT(3) // Over-Current Active
123#define PORTSC_RESET BIT(4) // Port Reset
124#define PORTSC_PR BIT(4) // Port Reset
125#define PORTSC_PLSE BIT(5) // Port Link State Enable
126#define PORTSC_PRES BIT(6) // Port Resume
127#define PORTSC_PP BIT(9) // Port Power
128#define PORTSC_SPEED_MASK (0xF << 10) // Bits 10–13: Port Speed
129#define PORTSC_SPEED_SHIFT 10
130
131#define PORTSC_PLS_SHIFT 5
132#define PORTSC_PLS_MASK (0xF << 5)
133#define PORTSC_LWS BIT(16) // Link Write Strobe
134#define PORTSC_CSC BIT(17) // Connect Status Change
135#define PORTSC_PEC BIT(18) // Port Enable/Disable Change
136#define PORTSC_WRC BIT(19) // Warm Port Reset Change
137#define PORTSC_OCC BIT(20) // Over-current Change
138#define PORTSC_PRC BIT(21) // Port Reset Change
139#define PORTSC_PLC BIT(22) // Port Link State Change
140#define PORTSC_CEC BIT(23) // Port Config Error Change
141
142#define PORTSC_PLS_POLLING 7
143#define PORTSC_PLS_U0 0
144#define PORTSC_PLS_U2 2
145#define PORTSC_PLS_U3 3
146#define PORTSC_PLS_RXDETECT 5
147
148#define PORTSC_IND BIT(24) // Port Indicator Control
149#define PORTSC_LWS_BIT BIT(16) // Link Write Strobe
150#define PORTSC_DR BIT(30) // Device Removable
151#define PORTSC_WPR BIT(31) // Warm Port Reset
152
153#define PORT_SPEED_FULL 1 // USB 1.1 Full Speed
154#define PORT_SPEED_LOW 2 // USB 1.1 Low Speed
155#define PORT_SPEED_HIGH 3 // USB 2.0 High Speed
156#define PORT_SPEED_SUPER 4 // USB 3.0 SuperSpeed
157#define PORT_SPEED_SUPER_PLUS 5 // USB 3.1 Gen2 (SuperSpeed+)
158
159#define CC_SUCCESS 1
160#define CC_DATA_BUFFER_ERROR 2
161#define CC_BABBLE_DETECTED 3
162#define CC_USB_TRANSACTION_ERROR 4
163#define CC_TRB_ERROR 5
164#define CC_STALL_ERROR 6
165#define CC_RESOURCE_ERROR 7
166#define CC_BANDWIDTH_ERROR 8
167#define CC_NO_SLOTS_AVAILABLE 9
168#define CC_INVALID_STREAM_TYPE 10
169#define CC_SLOT_NOT_ENABLED_ERROR 11
170#define CC_ENDPOINT_NOT_ENABLED 12
171#define CC_SHORT_PACKET 13
172#define CC_RING_UNDERRUN 14
173#define CC_RING_OVERRUN 15
174#define CC_VF_EVENT_RING_FULL_ERROR 16
175#define CC_PARAMETER_ERROR 17
176#define CC_BANDWIDTH_OVERRUN_ERROR 18
177#define CC_CONTEXT_STATE_ERROR 19
178#define CC_NO_PING_RESPONSE_ERROR 20
179#define CC_EVENT_RING_FULL 21
180#define CC_INCOMPATIBLE_DEVICE 22
181#define CC_MISSED_SERVICE 23
182#define CC_COMMAND_RING_STOPPED 24
183#define CC_COMMAND_ABORTED 25
184#define CC_STOPPED 26
185#define CC_STOPPED_LEN_INVALID 27
186#define CC_STOPPED_SHORT_PACKET 28
187#define CC_MAX_EXIT_LATENCY_TOO_LARGE 29
188
189LOG_HANDLE_EXTERN(xhci);
190LOG_SITE_EXTERN(xhci);
191#define xhci_log(log_level, fmt, ...) \
192 log(LOG_SITE(xhci), LOG_HANDLE(xhci), log_level, fmt, ##__VA_ARGS__)
193#define xhci_warn(fmt, ...) xhci_log(LOG_WARN, fmt, ##__VA_ARGS__)
194#define xhci_error(fmt, ...) xhci_log(LOG_ERROR, fmt, ##__VA_ARGS__)
195#define xhci_info(fmt, ...) xhci_log(LOG_INFO, fmt, ##__VA_ARGS__)
196#define xhci_debug(fmt, ...) xhci_log(LOG_DEBUG, fmt, ##__VA_ARGS__)
197#define xhci_trace(fmt, ...) xhci_log(LOG_TRACE, fmt, ##__VA_ARGS__)
198
199/*
200 * Lifetime invariant:
201 * - Slot refcount > 0 implies:
202 * - Slot is ENABLED or DISCONNECTING
203 * - Endpoint rings may exist
204 * - When slot refcount reaches 0:
205 * - Disable Slot has completed
206 * - No TRBs may be issued
207 * - All memory may be freed
208 */
209
210// 5.3: XHCI Capability Registers
211/* NOTE: offsets and sizes in kernel/drivers/xhci/layout.c */
212struct xhci_cap_regs {
213 uint8_t cap_length;
214 uint8_t reserved;
215 uint16_t hci_version;
216 uint32_t hcs_params1;
217 uint32_t hcs_params2;
218 uint32_t hcs_params3;
219 uint32_t hcc_params1;
220 uint32_t dboff;
221 uint32_t rtsoff;
222 uint32_t hcc_params2;
223} cc_packed;
224
225struct xhci_port_regs {
226 uint32_t portsc; // Port Status and Control
227 uint32_t portpmsc; // Port Power Management Status and Control
228 uint32_t portli; // Port Link Info
229 uint32_t portct; // Port Configuration Timeout
230};
231
232struct xhci_usbcmd {
233 union {
234 uint32_t raw;
235 struct {
236 uint32_t run_stop : 1;
237 uint32_t host_controller_reset : 1;
238 uint32_t interrupter_enable : 1;
239 uint32_t host_system_error_en : 1;
240 uint32_t reserved0 : 3;
241 uint32_t light_host_controller_reset : 1;
242 uint32_t controller_save_state : 1;
243 uint32_t controller_restore_state : 1;
244
245 uint32_t enable_wrap_event : 1;
246 uint32_t enable_u3_mf_index : 1;
247 uint32_t reserved1 : 1;
248
249 uint32_t cem_enable : 1;
250 uint32_t extended_tbc_enable : 1;
251
252 uint32_t extended_tbc_trb_status_enable : 1;
253
254 uint32_t vtio_enable : 1;
255
256 uint32_t reserved2 : 15;
257 };
258 };
259} cc_packed;
260/* Page 444 */
261struct xhci_slot_ctx {
262 uint32_t route_string : 20; // Location in USB topology
263
264 uint32_t speed : 4; // Speed of the device
265
266 uint32_t reserved0 : 1;
267
268 uint32_t mtt : 1; /* Set to '1' by software
269 * if this is a high speed hub that
270 * supports multiple TTs*/
271
272 uint32_t hub : 1; /* Set to '1' by software
273 * if this is a USB hub, 0 if
274 * function */
275
276 uint32_t context_entries : 5; /* Index of the last
277 * valid endpoint context
278 * within this structure */
279
280 uint32_t max_exit_latency : 16; /* In microseconds,
281 * worst case time it takes
282 * to wake up all links
283 * in path to device*/
284
285 uint32_t root_hub_port : 8; /* Root hub port number used to
286 * access the USB device */
287
288 uint32_t num_ports : 8; /* If this is a hub,
289 * this is set by software to
290 * identify downstream ports
291 * supported by the hub */
292
293 uint32_t parent_hub_slot_id : 8; /* Slot ID of the
294 * parent high-speed hub */
295
296 uint32_t parent_port_number : 8; /* Port number of the
297 * parent high-speed hub */
298
299 uint32_t parent_think_time : 2; /* Think time of the
300 * parent high-speed hub */
301
302 uint32_t reserved1 : 4;
303
304 uint32_t interrupter_target : 10; /* Index of the interrupter to events
305 * generated by this slot */
306
307 uint32_t usb_device_address : 8; /* Address of USB device assigned by xHC */
308 uint32_t reserved2 : 19;
309 uint32_t slot_state : 5; /* 0 - disabled/enabled, 1 - default, 2 -
310 * addressed, 3 - configured, rest reserved*/
311 uint32_t reserved3[4];
312} cc_packed;
313struct xhci_ep_ctx { // Refer to page 450 of the XHCI specification
314
315 uint32_t ep_state : 3; /* The current operational state of the endpoint
316 * 0 - Disabled (non-operational)
317 * 1 - Running
318 * 2 - Halted
319 * 3 - Stopped
320 * 4 - Error - SW can manipulate the transfer ring
321 * 5-7 - Reserved
322 */
323
324 uint32_t reserved1 : 5;
325
326 uint32_t mult : 2; /* Maximum number of bursts in an interval
327 * that this endpoint supports.
328 * Zero-based value, 0-3 is 1-4 bursts
329 * 0 for all endpoint types except SS Isochronous
330 */
331
332 uint32_t max_pstreams : 5; /* Maximum Primary streams this endpoint
333 * supports. If this is '0', the TR
334 * dequeue pointer should point to a
335 * transfer ring.
336 * If this is > '0' the TR dequeue
337 * pointer points to a Primary Stream Context
338 * Array.
339 */
340
341 uint32_t lsa : 1; /* Linear Stream Array, identifies how
342 * an ID stream is interpreted
343 * '1' disables Secondary Stream Arrays
344 * Linear index into Primary Stream Array
345 * Valid values are MaxPstreams 1 - 15
346 */
347
348 uint32_t interval : 8; /* Period between consecutive requests
349 * to a USB endpoint, expressed in 125 microsecond
350 * increments. Interval of 0 means period of 125us.
351 * A value of 1 means a period of 250us, etc.
352 */
353
354 uint32_t max_esit_payload_hi : 8; /* Max Endpoint Service Time
355 * Interval Payload High
356 * If LEC is '1' this is the high order
357 * 8 bits of the max ESIT payload value.
358 * If this is '0', then this is reserved
359 */
360
361 uint32_t reserved2 : 1;
362
363 uint32_t error_count : 2; /* Two bit down count, identifying the number
364 * of consecutive USB-bus errors allowed
365 * while executing a TD.
366 */
367
368 uint32_t ep_type : 3; /* Endpoint type
369 * 0 - Not valid
370 * 1 - Isochronous Out
371 * 2 - Bulk Out
372 * 3 - Interrupt Out
373 * 4 - Control Bidirectional
374 * 5 - Isochronous In
375 * 6 - Bulk In
376 * 7 - Interrupt In
377 */
378
379 uint32_t reserved3 : 1;
380 uint32_t host_initiate_disable : 1; /* The field affects Stream enabled
381 * endpoints allowing the HI stream
382 * selection feature to be disabled for
383 * the endpoint. Setting to '1' disables
384 * the HI stream selection feature. '0'
385 * enables normal stream operation
386 */
387
388 uint32_t max_burst_size : 8; /* Maximum number of consecutive USB
389 * transactions per scheduling opportunity.
390 * 0-based, 0-15 means 1-16
391 */
392
393 uint32_t max_packet_size : 16; /* Max packet size in bytes that this
394 * endpoint is capable of sending or
395 * receiving when configured.
396 */
397
398 union {
399 uint64_t dequeue_ptr_raw;
400 struct {
401 uint32_t dcs : 1; /* Dequeue cycle state - value of the xHC CCS
402 * (Consumer Cycle State) flag for the TRB
403 * referenced by the TR Dequeue pointer.
404 * '0' if `max_pstreams` > '0'
405 */
406
407 uint32_t reserved4 : 3;
408
409 uint64_t dequeue_ptr : 60; /* dequeue pointer
410 * MUST be aligned to 16 BYTE BOUNDARY
411 */
412 };
413 };
414
415 uint32_t average_trb_length : 16; /* Average length of TRBs executed
416 * by this endpoint. Must be > '0'
417 */
418
419 uint32_t max_esit_payload_lo : 16; /* Low order 16 bits of
420 * max ESIT payload.
421 * Represends the total
422 * number of bytes
423 * this endpoint will
424 * transfer during an ESIT
425 */
426 uint32_t reserved5[3];
427} cc_packed;
428struct xhci_input_ctrl_ctx { // Refer to page 461 of the XHCI specification
429
430 uint32_t drop_flags; /* Single bitfields to identify which
431 * device context data structs
432 * should be disabled by command.
433 * '1' disables the respective EP CTX.
434 *
435 * First two bits reserved
436 */
437
438 uint32_t add_flags; /* Single bitfields to identify
439 * which device CTX data structures
440 * should be evaluated or enabled
441 * by command. '1' enables the respective
442 * CTX
443 */
444
445 uint32_t reserved[5];
446
447 uint32_t config : 8; /* If CIC = '1' and CIE = '1', and this input CTX
448 * is associated with a Configure Endpoint command,
449 * this field contains the value
450 * of the Standard Configuration Descriptor
451 * bConfiguration field associated with this command.
452 * Otherwise, clear to '0'
453 */
454
455 uint32_t interface_num : 8; /* If CIC = '1' and CIE = '1',
456 * and this input CTX
457 * is associated with a
458 * Configure Endpoint
459 * Command, and this command
460 * was issued due to a
461 * SET_INTERFACE request,
462 * this contains the
463 * Standard Interface
464 * Descriptor bInterfaceNumber
465 * field associated with the command.
466 * Otherwise, clear to '0'
467 */
468
469 uint32_t alternate_setting : 8; /* If CIC = '1' and CIE = '1',
470 * and this input CTX is associated
471 * with a Configure Endpoint command,
472 * and the command was issued due
473 * to a SET_INTERFACE request,
474 * then this field contains
475 * the value of the Standard
476 * Interface Descriptor bAlternateSetting
477 * field associated with the
478 * command. Otherwise, clear to '0'.
479 */
480
481 uint32_t reserved1 : 8;
482} cc_packed;
483struct xhci_input_ctx { // Refer to page 460 of the XHCI Spec
484 struct xhci_input_ctrl_ctx ctrl_ctx;
485 struct xhci_slot_ctx slot_ctx;
486 struct xhci_ep_ctx ep_ctx[31];
487} cc_packed;
488struct xhci_device_ctx {
489 struct xhci_slot_ctx slot_ctx;
490 struct xhci_ep_ctx ep_ctx[32]; // Endpoint 1–31 (ep0 separate)
491} cc_packed;
492
493struct xhci_op_regs {
494 struct xhci_usbcmd usbcmd;
495 uint32_t usbsts;
496 uint32_t pagesize;
497 uint32_t reserved[2];
498 uint32_t dnctrl;
499 uint64_t crcr;
500 uint32_t reserved2[4];
501 uint64_t dcbaap;
502 uint32_t config;
503 uint32_t reserved3[241];
504 struct xhci_port_regs regs[];
505};
506
507struct xhci_trb {
508 uint64_t parameter;
509 uint32_t status;
510 uint32_t control;
511} cc_packed;
512struct xhci_ring {
513 struct xhci_trb *trbs; /* Virtual mapped TRB buffer */
514 uint64_t phys; /* Physical address of TRB buffer */
515 uint32_t enqueue_index; /* Next TRB to fill */
516 uint32_t dequeue_index; /* Point where controller sends back things */
517 uint8_t cycle; /* Cycle bit, toggles after ring wrap */
518 uint32_t size; /* Number of TRBs in ring */
519 size_t outgoing;
520};
521
522struct xhci_erst_entry {
523 uint64_t ring_segment_base;
524 uint32_t ring_segment_size;
525 uint32_t reserved;
526} cc_packed;
527
528#define XHCI_ERDP_EHB_BIT BIT(3)
529
530/* Page 424 */
531struct xhci_interrupter_regs {
532 uint32_t iman; /* Interrupt management */
533 uint32_t imod; /* Interrupt moderation */
534 uint32_t erstsz; /* Event Ring Segment Table Size */
535 uint32_t reserved;
536 uint64_t erstba; /* Event Ring Segment Table Base Address */
537 uint64_t erdp;
538
539} cc_packed;
540
541struct xhci_dcbaa { // Device context base address array - check page 441
542 uint64_t ptrs[256];
543} cc_aligned(64);
544
545struct xhci_ext_cap {
546 uint8_t cap_id;
547 uint8_t next;
548 uint16_t cap_specific;
549};
550
551enum xhci_slot_state {
552 XHCI_SLOT_STATE_UNDEF,
553 XHCI_SLOT_STATE_ENABLED,
554 XHCI_SLOT_STATE_DISCONNECTING,
555 XHCI_SLOT_STATE_DISCONNECTED,
556};
557
558static inline const char *xhci_slot_state_str(enum xhci_slot_state s) {
559 switch (s) {
560 case XHCI_SLOT_STATE_UNDEF: return "SLOT UNDEF";
561 case XHCI_SLOT_STATE_ENABLED: return "SLOT ENABLED";
562 case XHCI_SLOT_STATE_DISCONNECTING: return "SLOT DISCONNECTING";
563 case XHCI_SLOT_STATE_DISCONNECTED: return "SLOT DISCONNECTED";
564 default: return "SLOT UNKNOWN";
565 }
566}
567
568enum xhci_port_state {
569 XHCI_PORT_STATE_UNDEF,
570 XHCI_PORT_STATE_CONNECTING,
571 XHCI_PORT_STATE_CONNECTED,
572 XHCI_PORT_STATE_DISCONNECTING,
573 XHCI_PORT_STATE_DISCONNECTED,
574};
575
576static inline const char *xhci_port_state_str(enum xhci_port_state s) {
577 switch (s) {
578 case XHCI_PORT_STATE_UNDEF: return "PORT UNDEF";
579 case XHCI_PORT_STATE_CONNECTING: return "PORT CONNECTING";
580 case XHCI_PORT_STATE_CONNECTED: return "PORT CONNECTED";
581 case XHCI_PORT_STATE_DISCONNECTING: return "PORT DISCONNECTING";
582 case XHCI_PORT_STATE_DISCONNECTED: return "PORT DISCONNECTED";
583 default: return "PORT UNKNOWN";
584 }
585}
586
587struct xhci_slot {
588 atomic(enum xhci_slot_state) state;
589 struct xhci_device *dev;
590 struct xhci_ring *ep_rings[32];
591 uint8_t slot_id; /* Just so everyone knows what slot we are */
592
593 /* As soon as this drops to zero we clear the ep_rings */
594 refcount_t refcount;
595 struct xhci_port *port;
596 struct usb_device *udev;
597};
598
599struct xhci_port {
600 /* Raw spinlock to protect against concurrent updating */
601 struct spinlock update_lock;
602 uint8_t port_id;
603 struct xhci_slot *slot;
604 uint8_t speed;
605 bool usb3;
606 uint64_t generation;
607 enum xhci_port_state state;
608 struct xhci_device *dev;
609};
610
611enum xhci_request_status {
612 /* The first 3 statuses indicate list state.
613 *
614 * OUTGOING requests have a TRB, and have rang the doorbell.
615 *
616 * WAITING requests cannot be currently satisfied because the
617 * command ring is full.
618 *
619 * PROCESSED requests have been handled by the ISR with a success state.
620 * Technically they run in the worker thread but the status is set from ISR.
621 *
622 * DISCONNECT requests occur when a port is disconnected and the request
623 * no longer goes anywhere (because the port is gone)
624 */
625 XHCI_REQUEST_SENDING,
626 XHCI_REQUEST_OK,
627 XHCI_REQUEST_CANCELLED,
628 XHCI_REQUEST_DISCONNECT,
629 XHCI_REQUEST_ERR,
630};
631
632enum xhci_request_list {
633 XHCI_REQ_LIST_NONE,
634 XHCI_REQ_LIST_OUTGOING,
635 XHCI_REQ_LIST_WAITING,
636 XHCI_REQ_LIST_PROCESSED,
637 XHCI_REQ_LIST_MAX,
638};
639
640enum xhci_request_command_type { /* Abstract command types, not 1:1 */
641 XHCI_CMD_TYPE_NONE,
642 XHCI_CMD_TYPE_ENABLE_SLOT,
643 XHCI_CMD_TYPE_DISABLE_SLOT,
644 XHCI_CMD_TYPE_ADDRESS_DEVICE,
645 XHCI_CMD_TYPE_CONFIGURE_ENDPOINT,
646 XHCI_CMD_TYPE_EVALUATE_CONTEXT,
647 XHCI_CMD_TYPE_RESET_ENDPOINT,
648 XHCI_CMD_TYPE_STOP_ENDPOINT,
649 XHCI_CMD_TYPE_SET_TR_DEQUEUE_POINTER,
650 XHCI_CMD_TYPE_RESET_DEVICE,
651 XHCI_CMD_TYPE_FORCE_EVENT,
652 XHCI_CMD_TYPE_INTERRUPT_TRANSFER,
653 XHCI_CMD_TYPE_CONTROL_TRANSFER,
654 XHCI_CMD_TYPE_NO_OP,
655 XHCI_CMD_TYPE_NORMAL, /* 'misc.' */
656};
657
658struct xhci_device {
659 irq_t irq; /* What IRQ line have we routed to this? */
660 struct pci_device *pci;
661 struct xhci_input_ctx *input_ctx;
662 struct xhci_cap_regs cc_mem_io *cap_regs; /* Capability registers */
663 struct xhci_op_regs cc_mem_io *op_regs; /* Operational registers */
664 struct xhci_interrupter_regs cc_mem_io *intr_regs; /* Interrupter regs */
665
666 struct xhci_dcbaa *dcbaa;
667
668 struct xhci_ring *event_ring;
669 struct xhci_ring *cmd_ring;
670 struct xhci_erst_entry *erst;
671
672 struct xhci_port_regs cc_mem_io *port_regs;
673 uint64_t ports;
674 struct xhci_slot slots[XHCI_SLOT_COUNT];
675 struct xhci_port port_info[XHCI_PORT_COUNT];
676
677 struct list_head requests[XHCI_REQ_LIST_MAX];
678
679 size_t num_devices;
680 struct list_head devices;
681 struct spinlock lock;
682 struct semaphore sem;
683 struct semaphore port_disconnect;
684 struct semaphore port_connect;
685 struct usb_controller *controller;
686 atomic_bool worker_waiting;
687};
688
689struct xhci_command {
690 struct xhci_ring *ring; /* what ring? */
691 struct xhci_slot *slot;
692 uint32_t ep_id;
693
694 size_t num_trbs;
695 void (*emit)(struct xhci_command *cmd, struct xhci_ring *ring);
696
697 struct xhci_request *request; /* associated request */
698 void *private;
699};
700
701struct xhci_request {
702 struct event event;
703 /* Tied back to the USB request */
704 enum xhci_request_command_type type;
705 enum xhci_request_list list_owner;
706 struct usb_request *urb;
707 struct xhci_command *command;
708
709 struct xhci_trb *last_trb;
710 uint64_t trb_phys;
711 uint8_t port; /* What port is this for? Used to match
712 * requests on disconnect */
713
714 /* the raw completion code for this request */
715 volatile uint8_t completion_code;
716 volatile uint64_t return_parameter;
717 volatile uint32_t return_status;
718 volatile uint32_t return_control;
719 uint64_t generation;
720
721 volatile enum xhci_request_status status;
722
723 struct list_node list;
724 void (*callback)(struct xhci_device *, struct xhci_request *);
725 void *private;
726};
727
728struct xhci_return {
729 uint32_t control;
730 uint32_t status;
731};
732
733static inline const char *
734xhci_request_command_type_str(enum xhci_request_command_type t) {
735 switch (t) {
736 case XHCI_CMD_TYPE_NONE: return "CMD NONE";
737 case XHCI_CMD_TYPE_ENABLE_SLOT: return "CMD ENABLE SLOT";
738 case XHCI_CMD_TYPE_DISABLE_SLOT: return "CMD DISABLE SLOT";
739 case XHCI_CMD_TYPE_ADDRESS_DEVICE: return "CMD ADDRESS DEVICE";
740 case XHCI_CMD_TYPE_CONFIGURE_ENDPOINT: return "CMD CONFIGURE ENDPOINT";
741 case XHCI_CMD_TYPE_EVALUATE_CONTEXT: return "CMD EVALUATE CONTEXT";
742 case XHCI_CMD_TYPE_RESET_ENDPOINT: return "CMD RESET ENDPOINT";
743 case XHCI_CMD_TYPE_STOP_ENDPOINT: return "CMD STOP ENDPOINT";
744 case XHCI_CMD_TYPE_SET_TR_DEQUEUE_POINTER: return "CMD SET TR DEQUEUE PTR";
745 case XHCI_CMD_TYPE_RESET_DEVICE: return "CMD RESET DEVICE";
746 case XHCI_CMD_TYPE_FORCE_EVENT: return "CMD FORCE EVENT";
747 case XHCI_CMD_TYPE_INTERRUPT_TRANSFER: return "CMD INTERRUPT TRANSFER";
748 case XHCI_CMD_TYPE_CONTROL_TRANSFER: return "CMD CONTROL TRANSFER";
749 case XHCI_CMD_TYPE_NO_OP: return "CMD NO OP";
750 case XHCI_CMD_TYPE_NORMAL: return "CMD NORMAL";
751 default: return "CMD UNKNOWN";
752 }
753}
754
755void xhci_init(uint8_t bus, uint8_t slot, uint8_t func, struct pci_device *dev);
756