LAPIC
include/acpi/lapic.h View source View on GitHubFunctions
Section titled “Functions”lapic_reg_to_x2apic_msr
Section titled “lapic_reg_to_x2apic_msr”uint32_t lapic_reg_to_x2apic_msr(uint32_t reg);lapic_write
Section titled “lapic_write”void lapic_write(uint32_t reg, uint32_t val);lapic_read
Section titled “lapic_read”uint32_t lapic_read(uint32_t reg);lapic_init
Section titled “lapic_init”void lapic_init();lapic_timer_init
Section titled “lapic_timer_init”void lapic_timer_init(cpu_id_t core_id);lapic_get_id
Section titled “lapic_get_id”uint64_t lapic_get_id(void);cpu_get_this_id
Section titled “cpu_get_this_id”uint32_t cpu_get_this_id(void);lapic_timer_disable
Section titled “lapic_timer_disable”void lapic_timer_disable();lapic_timer_is_enabled
Section titled “lapic_timer_is_enabled”bool lapic_timer_is_enabled();lapic_timer_enable
Section titled “lapic_timer_enable”void lapic_timer_enable();lapic_timer_set_ms
Section titled “lapic_timer_set_ms”void lapic_timer_set_ms(uint32_t ms);panic_broadcast
Section titled “panic_broadcast”void panic_broadcast(size_t exclude_core);x2apic_init
Section titled “x2apic_init”void x2apic_init();ipi_send
Section titled “ipi_send”void ipi_send(uint32_t apic_id, uint8_t vector);nmi_send
Section titled “nmi_send”void nmi_send(uint32_t apic_id);lapic_get_chip
Section titled “lapic_get_chip”struct irq_chip * lapic_get_chip();Variables
Section titled “Variables”extern uint32_t *lapic;x2apic_enabled
Section titled “x2apic_enabled”extern bool x2apic_enabled;Macros
Section titled “Macros”LAPIC_ICR_LOW
Section titled “LAPIC_ICR_LOW”#define LAPIC_ICR_LOW 0x300LAPIC_ICR_HIGH
Section titled “LAPIC_ICR_HIGH”#define LAPIC_ICR_HIGH 0x310LAPIC_DELIVERY_FIXED
Section titled “LAPIC_DELIVERY_FIXED”#define LAPIC_DELIVERY_FIXED (0x0 << 8)LAPIC_DELIVERY_LOWEST
Section titled “LAPIC_DELIVERY_LOWEST”#define LAPIC_DELIVERY_LOWEST (0x1 << 8)LAPIC_DELIVERY_SMI
Section titled “LAPIC_DELIVERY_SMI”#define LAPIC_DELIVERY_SMI (0x2 << 8)LAPIC_DELIVERY_NMI
Section titled “LAPIC_DELIVERY_NMI”#define LAPIC_DELIVERY_NMI (0x4 << 8)LAPIC_DELIVERY_INIT
Section titled “LAPIC_DELIVERY_INIT”#define LAPIC_DELIVERY_INIT (0x5 << 8)LAPIC_DELIVERY_STARTUP
Section titled “LAPIC_DELIVERY_STARTUP”#define LAPIC_DELIVERY_STARTUP (0x6 << 8)LAPIC_LEVEL_ASSERT
Section titled “LAPIC_LEVEL_ASSERT”#define LAPIC_LEVEL_ASSERT (1 << 14)LAPIC_TRIGGER_EDGE
Section titled “LAPIC_TRIGGER_EDGE”#define LAPIC_TRIGGER_EDGE (0 << 15)LAPIC_TRIGGER_LEVEL
Section titled “LAPIC_TRIGGER_LEVEL”#define LAPIC_TRIGGER_LEVEL (1 << 15)LAPIC_IPI_IN_FLIGHT
Section titled “LAPIC_IPI_IN_FLIGHT”#define LAPIC_IPI_IN_FLIGHT (1u << 12)LAPIC_DEST_PHYSICAL
Section titled “LAPIC_DEST_PHYSICAL”#define LAPIC_DEST_PHYSICAL (0 << 11)LAPIC_DEST_LOGICAL
Section titled “LAPIC_DEST_LOGICAL”#define LAPIC_DEST_LOGICAL (1 << 11)LAPIC_DEST_SHIFT
Section titled “LAPIC_DEST_SHIFT”#define LAPIC_DEST_SHIFT 24LAPIC_REG_ID
Section titled “LAPIC_REG_ID”#define LAPIC_REG_ID 0x020LAPIC_REG_EOI
Section titled “LAPIC_REG_EOI”#define LAPIC_REG_EOI 0x0B0LAPIC_REG_SVR
Section titled “LAPIC_REG_SVR”#define LAPIC_REG_SVR 0x0F0LAPIC_REG_LVT_TIMER
Section titled “LAPIC_REG_LVT_TIMER”#define LAPIC_REG_LVT_TIMER 0x320LAPIC_REG_TIMER_INIT
Section titled “LAPIC_REG_TIMER_INIT”#define LAPIC_REG_TIMER_INIT 0x380LAPIC_REG_TIMER_CUR
Section titled “LAPIC_REG_TIMER_CUR”#define LAPIC_REG_TIMER_CUR 0x390LAPIC_REG_TIMER_DIV
Section titled “LAPIC_REG_TIMER_DIV”#define LAPIC_REG_TIMER_DIV 0x3E0LAPIC_LVT_MASK
Section titled “LAPIC_LVT_MASK”#define LAPIC_LVT_MASK (1 << 16)LAPIC_ENABLE
Section titled “LAPIC_ENABLE”#define LAPIC_ENABLE 0x100LAPIC_SPURIOUS_REGISTER
Section titled “LAPIC_SPURIOUS_REGISTER”#define LAPIC_SPURIOUS_REGISTER 0xF0IA32_X2APIC_BASE
Section titled “IA32_X2APIC_BASE”#define IA32_X2APIC_BASE 0x800IA32_X2APIC_ID
Section titled “IA32_X2APIC_ID”#define IA32_X2APIC_ID (IA32_X2APIC_BASE + 0x02)IA32_X2APIC_EOI
Section titled “IA32_X2APIC_EOI”#define IA32_X2APIC_EOI (IA32_X2APIC_BASE + 0x0B)IA32_X2APIC_SVR
Section titled “IA32_X2APIC_SVR”#define IA32_X2APIC_SVR (IA32_X2APIC_BASE + 0x0F)IA32_X2APIC_LVT_TIMER
Section titled “IA32_X2APIC_LVT_TIMER”#define IA32_X2APIC_LVT_TIMER (IA32_X2APIC_BASE + 0x32)IA32_X2APIC_TIMER_INIT
Section titled “IA32_X2APIC_TIMER_INIT”#define IA32_X2APIC_TIMER_INIT (IA32_X2APIC_BASE + 0x38)IA32_X2APIC_TIMER_CUR
Section titled “IA32_X2APIC_TIMER_CUR”#define IA32_X2APIC_TIMER_CUR (IA32_X2APIC_BASE + 0x39)IA32_X2APIC_TIMER_DIV
Section titled “IA32_X2APIC_TIMER_DIV”#define IA32_X2APIC_TIMER_DIV (IA32_X2APIC_BASE + 0x3E)TIMER_VECTOR
Section titled “TIMER_VECTOR”#define TIMER_VECTOR 0x20TIMER_MODE_PERIODIC
Section titled “TIMER_MODE_PERIODIC”#define TIMER_MODE_PERIODIC (1 << 17)IA32_APIC_BASE
Section titled “IA32_APIC_BASE”#define IA32_APIC_BASE 0x1BAPIC_X2APIC_ENABLE
Section titled “APIC_X2APIC_ENABLE”#define APIC_X2APIC_ENABLE (1 << 10)IA32_X2APIC_ICR
Section titled “IA32_X2APIC_ICR”#define IA32_X2APIC_ICR 0x830LAPIC_LEVEL_ASSERT
Section titled “LAPIC_LEVEL_ASSERT”#define LAPIC_LEVEL_ASSERT (1 << 14)IA32_APIC_BASE_MSR
Section titled “IA32_APIC_BASE_MSR”#define IA32_APIC_BASE_MSR 0x1BIA32_APIC_BASE_MASK
Section titled “IA32_APIC_BASE_MASK”#define IA32_APIC_BASE_MASK 0xFFFFF000ULIA32_APIC_BASE_ENABLE
Section titled “IA32_APIC_BASE_ENABLE”#define IA32_APIC_BASE_ENABLE (1 << 11)