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LAPIC

include/acpi/lapic.h View source View on GitHub

Functions

Section titled “Functions”

lapic_reg_to_x2apic_msr

Section titled “lapic_reg_to_x2apic_msr”
uint32_t lapic_reg_to_x2apic_msr(uint32_t reg)
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lapic_write

Section titled “lapic_write”
void lapic_write(uint32_t reg, uint32_t val)
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lapic_read

Section titled “lapic_read”
uint32_t lapic_read(uint32_t reg)
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lapic_init

Section titled “lapic_init”
void lapic_init(void)
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x2apic_init

Section titled “x2apic_init”
void x2apic_init(void)
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lapic_get_id

Section titled “lapic_get_id”
uint64_t lapic_get_id(void)
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x2apic_get_id

Section titled “x2apic_get_id”
uint32_t x2apic_get_id(void)
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lapic_this_id

Section titled “lapic_this_id”
uint32_t lapic_this_id(void)
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lapic_dest_8bit

Section titled “lapic_dest_8bit”
uint8_t lapic_dest_8bit(uint32_t apic_id)
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IOAPIC entries and MSI addresses have 8 destination bits, larger ones need x2apic

lapic_get_chip

Section titled “lapic_get_chip”
struct irq_chip * lapic_get_chip(void)
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lapic_icr_write

Section titled “lapic_icr_write”
void lapic_icr_write(uint32_t dest, uint32_t lo)
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lapic_icr_try_write

Section titled “lapic_icr_try_write”
bool lapic_icr_try_write(uint32_t dest, uint32_t lo)
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Same as above, just the try version

lapic_icr_nmi_save

Section titled “lapic_icr_nmi_save”
uint32_t lapic_icr_nmi_save(void)
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NMIs happening between IPI sends can retarget the IPI

lapic_icr_nmi_restore

Section titled “lapic_icr_nmi_restore”
void lapic_icr_nmi_restore(uint32_t high)
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Variables

Section titled “Variables”

lapic

Section titled “lapic”
extern uint32_t cc_mem_io *lapic
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x2apic_enabled

Section titled “x2apic_enabled”
extern bool x2apic_enabled
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Macros

Section titled “Macros”

IA32_APIC_BASE

Section titled “IA32_APIC_BASE”
#define IA32_APIC_BASE 0x1B
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IA32_APIC_BASE_MSR

Section titled “IA32_APIC_BASE_MSR”
#define IA32_APIC_BASE_MSR 0x1B
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IA32_APIC_BASE_MASK

Section titled “IA32_APIC_BASE_MASK”
#define IA32_APIC_BASE_MASK 0xFFFFF000UL
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IA32_APIC_BASE_ENABLE

Section titled “IA32_APIC_BASE_ENABLE”
#define IA32_APIC_BASE_ENABLE BIT(11)
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APIC_X2APIC_ENABLE

Section titled “APIC_X2APIC_ENABLE”
#define APIC_X2APIC_ENABLE BIT(10)
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LAPIC_REG_ID

Section titled “LAPIC_REG_ID”
#define LAPIC_REG_ID 0x020
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LAPIC_REG_EOI

Section titled “LAPIC_REG_EOI”
#define LAPIC_REG_EOI 0x0B0
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LAPIC_REG_SVR

Section titled “LAPIC_REG_SVR”
#define LAPIC_REG_SVR 0x0F0
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LAPIC_REG_LVT_TIMER

Section titled “LAPIC_REG_LVT_TIMER”
#define LAPIC_REG_LVT_TIMER 0x320
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LAPIC_REG_TIMER_INIT

Section titled “LAPIC_REG_TIMER_INIT”
#define LAPIC_REG_TIMER_INIT 0x380
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LAPIC_REG_TIMER_CUR

Section titled “LAPIC_REG_TIMER_CUR”
#define LAPIC_REG_TIMER_CUR 0x390
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LAPIC_REG_TIMER_DIV

Section titled “LAPIC_REG_TIMER_DIV”
#define LAPIC_REG_TIMER_DIV 0x3E0
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LAPIC_LVT_MASK

Section titled “LAPIC_LVT_MASK”
#define LAPIC_LVT_MASK BIT(16)
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LAPIC_ENABLE

Section titled “LAPIC_ENABLE”
#define LAPIC_ENABLE 0x100
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LAPIC_SPURIOUS_REGISTER

Section titled “LAPIC_SPURIOUS_REGISTER”
#define LAPIC_SPURIOUS_REGISTER 0xF0
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TIMER_MODE_PERIODIC

Section titled “TIMER_MODE_PERIODIC”
#define TIMER_MODE_PERIODIC BIT(17)
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TIMER_MODE_ONESHOT

Section titled “TIMER_MODE_ONESHOT”
#define TIMER_MODE_ONESHOT (0 << 17)
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LAPIC_ICR_LOW

Section titled “LAPIC_ICR_LOW”
#define LAPIC_ICR_LOW 0x300
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LAPIC_ICR_HIGH

Section titled “LAPIC_ICR_HIGH”
#define LAPIC_ICR_HIGH 0x310
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LAPIC_DELIVERY_FIXED

Section titled “LAPIC_DELIVERY_FIXED”
#define LAPIC_DELIVERY_FIXED (0x0 << 8)
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LAPIC_DELIVERY_LOWEST

Section titled “LAPIC_DELIVERY_LOWEST”
#define LAPIC_DELIVERY_LOWEST (0x1 << 8)
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LAPIC_DELIVERY_SMI

Section titled “LAPIC_DELIVERY_SMI”
#define LAPIC_DELIVERY_SMI (0x2 << 8)
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LAPIC_DELIVERY_NMI

Section titled “LAPIC_DELIVERY_NMI”
#define LAPIC_DELIVERY_NMI (0x4 << 8)
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LAPIC_DELIVERY_INIT

Section titled “LAPIC_DELIVERY_INIT”
#define LAPIC_DELIVERY_INIT (0x5 << 8)
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LAPIC_DELIVERY_STARTUP

Section titled “LAPIC_DELIVERY_STARTUP”
#define LAPIC_DELIVERY_STARTUP (0x6 << 8)
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LAPIC_LEVEL_ASSERT

Section titled “LAPIC_LEVEL_ASSERT”
#define LAPIC_LEVEL_ASSERT BIT(14)
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LAPIC_TRIGGER_EDGE

Section titled “LAPIC_TRIGGER_EDGE”
#define LAPIC_TRIGGER_EDGE (0 << 15)
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LAPIC_TRIGGER_LEVEL

Section titled “LAPIC_TRIGGER_LEVEL”
#define LAPIC_TRIGGER_LEVEL BIT(15)
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LAPIC_IPI_IN_FLIGHT

Section titled “LAPIC_IPI_IN_FLIGHT”
#define LAPIC_IPI_IN_FLIGHT BIT(12)
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LAPIC_DEST_PHYSICAL

Section titled “LAPIC_DEST_PHYSICAL”
#define LAPIC_DEST_PHYSICAL (0 << 11)
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LAPIC_DEST_LOGICAL

Section titled “LAPIC_DEST_LOGICAL”
#define LAPIC_DEST_LOGICAL BIT(11)
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LAPIC_DEST_SHORTHAND_NONE

Section titled “LAPIC_DEST_SHORTHAND_NONE”
#define LAPIC_DEST_SHORTHAND_NONE (0x0 << 18)
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LAPIC_DEST_SHORTHAND_SELF

Section titled “LAPIC_DEST_SHORTHAND_SELF”
#define LAPIC_DEST_SHORTHAND_SELF (0x1 << 18)
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LAPIC_DEST_SHORTHAND_ALL

Section titled “LAPIC_DEST_SHORTHAND_ALL”
#define LAPIC_DEST_SHORTHAND_ALL (0x2 << 18)
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LAPIC_DEST_SHORTHAND_OTHERS

Section titled “LAPIC_DEST_SHORTHAND_OTHERS”
#define LAPIC_DEST_SHORTHAND_OTHERS (0x3 << 18)
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LAPIC_DEST_SHIFT

Section titled “LAPIC_DEST_SHIFT”
#define LAPIC_DEST_SHIFT 24
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X2APIC_CLUSTER_SHIFT

Section titled “X2APIC_CLUSTER_SHIFT”
#define X2APIC_CLUSTER_SHIFT 4
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LDR is read-only and derived from the ID. Cluster (ID[19:4]) in bits 31:16, one-hot ID[3:0] in bits 15:0

X2APIC_CLUSTER_SIZE

Section titled “X2APIC_CLUSTER_SIZE”
#define X2APIC_CLUSTER_SIZE BIT(X2APIC_CLUSTER_SHIFT)
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X2APIC_CLUSTER_ID_MASK

Section titled “X2APIC_CLUSTER_ID_MASK”
#define X2APIC_CLUSTER_ID_MASK 0xFFFF
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X2APIC_LDR_CLUSTER_SHIFT

Section titled “X2APIC_LDR_CLUSTER_SHIFT”
#define X2APIC_LDR_CLUSTER_SHIFT 16
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IA32_X2APIC_BASE

Section titled “IA32_X2APIC_BASE”
#define IA32_X2APIC_BASE 0x800
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IA32_X2APIC_ID

Section titled “IA32_X2APIC_ID”
#define IA32_X2APIC_ID (IA32_X2APIC_BASE + 0x02)
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IA32_X2APIC_EOI

Section titled “IA32_X2APIC_EOI”
#define IA32_X2APIC_EOI (IA32_X2APIC_BASE + 0x0B)
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IA32_X2APIC_SVR

Section titled “IA32_X2APIC_SVR”
#define IA32_X2APIC_SVR (IA32_X2APIC_BASE + 0x0F)
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IA32_X2APIC_ICR

Section titled “IA32_X2APIC_ICR”
#define IA32_X2APIC_ICR (IA32_X2APIC_BASE + 0x30)
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IA32_X2APIC_LVT_TIMER

Section titled “IA32_X2APIC_LVT_TIMER”
#define IA32_X2APIC_LVT_TIMER (IA32_X2APIC_BASE + 0x32)
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IA32_X2APIC_TIMER_INIT

Section titled “IA32_X2APIC_TIMER_INIT”
#define IA32_X2APIC_TIMER_INIT (IA32_X2APIC_BASE + 0x38)
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IA32_X2APIC_TIMER_CUR

Section titled “IA32_X2APIC_TIMER_CUR”
#define IA32_X2APIC_TIMER_CUR (IA32_X2APIC_BASE + 0x39)
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IA32_X2APIC_TIMER_DIV

Section titled “IA32_X2APIC_TIMER_DIV”
#define IA32_X2APIC_TIMER_DIV (IA32_X2APIC_BASE + 0x3E)
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