xHCI

include/drivers/xhci.h

struct `xhci_cap_regs`

Member Type	Member Name
`uint8_t`	`cap_length`
`uint8_t`	`reserved`
`uint16_t`	`hci_version`
`uint32_t`	`hcs_params1`
`uint32_t`	`hcs_params2`
`uint32_t`	`hcs_params3`
`uint32_t`	`hcc_params1`
`uint32_t`	`dboff`
`uint32_t`	`rtsoff`
`uint32_t`	`hcc_params2`

struct `xhci_port_regs`

Member Type	Member Name
`uint32_t`	`portsc`
`uint32_t`	`portpmsc`
`uint32_t`	`portli`
`uint32_t`	`portct`

union { uint32_t raw; struct { uint32_t run_stop : 1; uint32_t host_controller_reset : 1; uint32_t interrupter_enable : 1; uint32_t host_system_error_en : 1; uint32_t reserved0 : 3; uint32_t light_host_controller_reset : 1; uint32_t controller_save_state : 1; uint32_t controller_restore_state : 1; uint32_t enable_wrap_event : 1; uint32_t enable_u3_mf_index : 1; uint32_t reserved1 : 1; uint32_t cem_enable : 1; uint32_t extended_tbc_enable : 1; uint32_t extended_tbc_trb_status_enable : 1; uint32_t vtio_enable : 1; uint32_t reserved2 : 15; }; } None

Member Type	Member Name
union { uint32_t raw; struct { uint32_t run_stop : 1; uint32_t host_controller_reset : 1; uint32_t interrupter_enable : 1; uint32_t host_system_error_en : 1; uint32_t reserved0 : 3; uint32_t light_host_controller_reset : 1; uint32_t controller_save_state : 1; uint32_t controller_restore_state : 1; uint32_t enable_wrap_event : 1; uint32_t enable_u3_mf_index : 1; uint32_t reserved1 : 1; uint32_t cem_enable : 1; uint32_t extended_tbc_enable : 1; uint32_t extended_tbc_trb_status_enable : 1; uint32_t vtio_enable : 1; uint32_t reserved2 : 15; }; }	`None`

struct `xhci_slot_ctx`

Member Type	Member Name
`uint32_t`	`route_string`
`uint32_t`	`speed`
`uint32_t`	`reserved0`
`uint32_t`	`mtt`
`uint32_t`	`hub`
`uint32_t`	`context_entries`
`uint32_t`	`max_exit_latency`
`uint32_t`	`root_hub_port`
`uint32_t`	`num_ports`
`uint32_t`	`parent_hub_slot_id`
`uint32_t`	`parent_port_number`
`uint32_t`	`parent_think_time`
`uint32_t`	`reserved1`
`uint32_t`	`interrupter_target`
`uint32_t`	`usb_device_address`
`uint32_t`	`reserved2`
`uint32_t`	`slot_state`
`uint32_t`	`reserved3[4]`

struct `xhci_ep_ctx`

Member Type	Member Name
`uint32_t`	`ep_state`
`uint32_t`	`reserved1`
`uint32_t`	`mult`
`uint32_t`	`max_pstreams`
`uint32_t`	`lsa`
`uint32_t`	`interval`
`uint32_t`	`max_esit_payload_hi`
`uint32_t`	`reserved2`
`uint32_t`	`error_count`
`uint32_t`	`ep_type`
`uint32_t`	`reserved3`
`uint32_t`	`host_initiate_disable`
`uint32_t`	`max_burst_size`
`uint32_t`	`max_packet_size`
`union { uint64_t dequeue_ptr_raw; struct { uint32_t dcs : 1; /* Dequeue cycle state - value of the xHC CCS * (Consumer Cycle State) flag for the TRB * referenced by the TR Dequeue pointer. * '0' if` max_pstreams `> '0' / uint32_t reserved4 : 3; uint64_t dequeue_ptr : 60; / dequeue pointer * MUST be aligned to 16 BYTE BOUNDARY */ }; }`	`None`
`uint32_t`	`average_trb_length`
`uint32_t`	`max_esit_payload_lo`
`uint32_t`	`reserved5[3]`

struct `xhci_input_ctrl_ctx`

Member Type	Member Name
`uint32_t`	`drop_flags`
`uint32_t`	`add_flags`
`uint32_t`	`reserved[5]`
`uint32_t`	`config`
`uint32_t`	`interface_num`
`uint32_t`	`alternate_setting`
`uint32_t`	`reserved1`

struct `xhci_input_ctx`

Member Type	Member Name
`struct xhci_input_ctrl_ctx`	`ctrl_ctx`
`struct xhci_slot_ctx`	`slot_ctx`
`struct xhci_ep_ctx`	`ep_ctx[31]`

struct `xhci_device_ctx`

Member Type	Member Name
`struct xhci_slot_ctx`	`slot_ctx`
`struct xhci_ep_ctx`	`ep_ctx[32]`

struct `xhci_op_regs`

Member Type	Member Name
`struct xhci_usbcmd`	`usbcmd`
`uint32_t`	`usbsts`
`uint32_t`	`pagesize`
`uint32_t`	`reserved[2]`
`uint32_t`	`dnctrl`
`uint64_t`	`crcr`
`uint32_t`	`reserved2[4]`
`uint64_t`	`dcbaap`
`uint32_t`	`config`
`uint32_t`	`reserved3[241]`
`struct xhci_port_regs`	`regs[]`

struct `xhci_trb`

Member Type	Member Name
`uint64_t`	`parameter`
`uint32_t`	`status`
`uint32_t`	`control`

struct `xhci_ring`

Member Type	Member Name
`struct xhci_trb`	`*trbs`
`uint64_t`	`phys`
`uint32_t`	`enqueue_index`
`uint32_t`	`dequeue_index`
`uint8_t`	`cycle`
`uint32_t`	`size`
`size_t`	`outgoing`

struct `xhci_erst_entry`

Member Type	Member Name
`uint64_t`	`ring_segment_base`
`uint32_t`	`ring_segment_size`
`uint32_t`	`reserved`

struct `xhci_interrupter_regs`

Member Type	Member Name
`uint32_t`	`iman`
`uint32_t`	`imod`
`uint32_t`	`erstsz`
`uint32_t`	`reserved`
`uint64_t`	`erstba`
`uint64_t`	`erdp`

struct `xhci_dcbaa`

Member Type	Member Name
`uint64_t`	`ptrs[256]`

struct `xhci_ext_cap`

Member Type	Member Name
`uint8_t`	`cap_id`
`uint8_t`	`next`
`uint16_t`	`cap_specific`

struct `xhci_slot`

Member Type	Member Name
`enum xhci_slot_state`	`state`
`struct xhci_device`	`*dev`
`struct xhci_ring`	`*ep_rings[32]`
`uint8_t`	`slot_id`
`refcount_t`	`refcount`
`struct xhci_port`	`*port`
`struct usb_device`	`*udev`

struct `xhci_port`

Member Type	Member Name
`struct spinlock`	`update_lock`
`uint8_t`	`port_id`
`struct xhci_slot`	`*slot`
`uint8_t`	`speed`
`bool`	`usb3`
`uint64_t`	`generation`
`enum xhci_port_state`	`state`
`struct xhci_device`	`*dev`

struct `xhci_device`

Member Type	Member Name
`uint8_t`	`irq`
`struct pci_device`	`*pci`
`struct xhci_input_ctx`	`*input_ctx`
`struct xhci_cap_regs`	`*cap_regs`
`struct xhci_op_regs`	`*op_regs`
`struct xhci_interrupter_regs`	`*intr_regs`
`struct xhci_dcbaa`	`*dcbaa`
`struct xhci_ring`	`*event_ring`
`struct xhci_ring`	`*cmd_ring`
`struct xhci_erst_entry`	`*erst`
`struct xhci_port_regs`	`*port_regs`
`uint64_t`	`ports`
`struct xhci_slot`	`slots[XHCI_SLOT_COUNT]`
`struct xhci_port`	`port_info[XHCI_PORT_COUNT]`
`struct list_head`	`requests[XHCI_REQ_LIST_MAX]`
`size_t`	`num_devices`
`struct list_head`	`devices`
`struct spinlock`	`lock`
`struct semaphore`	`sem`
`struct semaphore`	`port_disconnect`
`struct semaphore`	`port_connect`
`struct usb_controller`	`*controller`
`atomic_bool`	`worker_waiting`

struct `xhci_command`

Member Type	Member Name
`struct xhci_ring`	`*ring`
`struct xhci_slot`	`*slot`
`uint32_t`	`ep_id`
`size_t`	`num_trbs`
`void`	`(emit)(struct xhci_command cmd, struct xhci_ring *ring)`
`struct xhci_request`	`*request`
`void`	`*private`

struct `xhci_request`

Member Type	Member Name
`enum xhci_request_list`	`list_owner`
`struct usb_request`	`*urb`
`struct xhci_command`	`*command`
`bool`	`slot_reset`
`struct xhci_trb`	`*last_trb`
`uint64_t`	`trb_phys`
`uint8_t`	`port`
`uint8_t`	`completion_code`
`uint64_t`	`return_parameter`
`uint32_t`	`return_status`
`uint32_t`	`return_control`
`uint64_t`	`generation`
`enum xhci_request_status`	`status`
`struct list_head`	`list`
`void`	`(callback)(struct xhci_device , struct xhci_request *)`
`void`	`*private`

struct `xhci_return`

Member Type	Member Name
`uint32_t`	`control`
`uint32_t`	`status`

enum `xhci_slot_state`

Name	Value
`XHCI_SLOT_STATE_UNDEF`	`None`
`XHCI_SLOT_STATE_ENABLED`	`None`
`XHCI_SLOT_STATE_DISCONNECTING`	`None`
`XHCI_SLOT_STATE_DISCONNECTED`	`None`

enum `xhci_port_state`

Name	Value
`XHCI_PORT_STATE_UNDEF`	`None`
`XHCI_PORT_STATE_CONNECTING`	`None`
`XHCI_PORT_STATE_CONNECTED`	`None`
`XHCI_PORT_STATE_DISCONNECTING`	`None`
`XHCI_PORT_STATE_DISCONNECTED`	`None`

enum `xhci_request_status`

Name	Value
`XHCI_REQUEST_SENDING`	`None`
`XHCI_REQUEST_OK`	`None`
`XHCI_REQUEST_CANCELLED`	`None`
`XHCI_REQUEST_DISCONNECT`	`None`
`XHCI_REQUEST_ERR`	`None`

enum `xhci_request_list`

Name	Value
`XHCI_REQ_LIST_NONE`	`None`
`XHCI_REQ_LIST_OUTGOING`	`None`
`XHCI_REQ_LIST_WAITING`	`None`
`XHCI_REQ_LIST_PROCESSED`	`None`
`XHCI_REQ_LIST_MAX`	`None`

static inline const char * xhci_slot_state_str(enum xhci_slot_state s)
static inline const char * xhci_port_state_str(enum xhci_port_state s)
void xhci_init(uint8_t bus,uint8_t slot,uint8_t func,struct pci_device *dev)

Defines

XHCI_DEVICE_TIMEOUT: 1000
TRB_RING_SIZE: 256
XHCI_PORT_COUNT: 64
XHCI_SLOT_COUNT: 255
XHCI_INPUT_CTX_ADD_FLAGS: ((1 << 0) | (1 << 1))
XHCI_SETUP_TRANSFER_TYPE_NONE: 0
XHCI_SETUP_TRANSFER_TYPE_OUT: 2
XHCI_SETUP_TRANSFER_TYPE_IN: 3
XHCI_USBSTS_HCH: 1 /* HC halted */
XHCI_USBSTS_HSE: (1 << 2) /* host system error */
XHCI_USBSTS_EI: (1 << 3) /* event interrupt */
XHCI_USBSTS_PCD: (1 << 4) /* port change detect */
XHCI_IMAN_MASK: 0x2
XHCI_IMAN_INT_PENDING: 0x1
XHCI_IMAN_INT_ENABLE: 0x2
XHCI_ENDPOINT_TYPE_INVAL: 0
XHCI_ENDPOINT_TYPE_ISOCH_OUT: 1
XHCI_ENDPOINT_TYPE_BULK_OUT: 2
XHCI_ENDPOINT_TYPE_INTERRUPT_OUT: 3
XHCI_ENDPOINT_TYPE_CONTROL_BI: 4
XHCI_ENDPOINT_TYPE_ISOCH_IN: 5
XHCI_ENDPOINT_TYPE_BULK_IN: 6
XHCI_ENDPOINT_TYPE_INTERRUPT_IN: 7
XHCI_EXT_CAP_ID_LEGACY_SUPPORT: 1
XHCI_EXT_CAP_ID_USB: 2
TRB_TYPE_RESERVED: 0x00
TRB_TYPE_NORMAL: 0x01
TRB_TYPE_SETUP_STAGE: 0x02
TRB_TYPE_DATA_STAGE: 0x03
TRB_TYPE_STATUS_STAGE: 0x04
TRB_TYPE_ISOCH: 0x05
TRB_TYPE_LINK: 0x06
TRB_TYPE_EVENT_DATA: 0x07
TRB_TYPE_NO_OP: 0x08
TRB_TYPE_NO_OP_COMMAND: 0x8
TRB_TYPE_ENABLE_SLOT: 0x09
TRB_TYPE_DISABLE_SLOT: 0x0A
TRB_TYPE_ADDRESS_DEVICE: 0x0B
TRB_TYPE_CONFIGURE_ENDPOINT: 0x0C
TRB_TYPE_EVALUATE_CONTEXT: 0x0D
TRB_TYPE_RESET_ENDPOINT: 0x0E
TRB_TYPE_STOP_ENDPOINT: 0x0F
TRB_TYPE_SET_TR_DEQUEUE_POINTER: 0x10
TRB_TYPE_RESET_DEVICE: 0x11
TRB_TYPE_FORCE_EVENT: 0x12
TRB_TYPE_NEGOTIATE_BW: 0x13
TRB_TYPE_SET_LATENCY_TOLERANCE: 0x14
TRB_TYPE_GET_PORT_BANDWIDTH: 0x15
TRB_TYPE_FORCE_HEADER: 0x16
TRB_TYPE_NO_OP_2_COMMAND: 0x17
TRB_TYPE_TRANSFER_EVENT: 0x20
TRB_TYPE_COMMAND_COMPLETION: 0x21
TRB_TYPE_PORT_STATUS_CHANGE: 0x22
TRB_TYPE_BANDWIDTH_REQUEST: 0x23
TRB_TYPE_DOORBELL_EVENT: 0x24
TRB_TYPE_HOST_CONTROLLER_EVENT: 0x25
TRB_TYPE_DEVICE_NOTIFICATION: 0x26
TRB_TYPE_MFINDEX_WRAP: 0x27
TRB_CYCLE_BIT: (1 << 0)
TRB_ENT_BIT: (1 << 1) // Evaluate Next TRB
TRB_ISP_BIT: (1 << 2) // Interrupt on Short Packet
TRB_NS_BIT: (1 << 3) // No Snoop
TRB_CH_BIT: (1 << 4) // Chain
TRB_IOC_BIT: (1 << 5) // Interrupt On Completion
TRB_IDT_BIT: (1 << 6) // Immediate Data
TRB_BEI_BIT: (1 << 9) // Block Event Interrupt (ISO)
TRB_TOGGLE_CYCLE_BIT: (1 << 1)
TRB_TYPE_SHIFT: 10
PORTSC_CCS: (1 << 0) // Current Connect Status
PORTSC_PED: (1 << 1) // Port Enabled/Disabled
PORTSC_OCA: (1 << 3) // Over-Current Active
PORTSC_RESET: (1 << 4) // Port Reset
PORTSC_PR: (1 << 4) // Port Reset
PORTSC_PLSE: (1 << 5) // Port Link State Enable
PORTSC_PRES: (1 << 6) // Port Resume
PORTSC_PP: (1 << 9) // Port Power
PORTSC_SPEED_MASK: (0xF << 10) // Bits 10–13: Port Speed
PORTSC_SPEED_SHIFT: 10
PORTSC_PLS_SHIFT: 5
PORTSC_PLS_MASK: (0xF << 5)
PORTSC_LWS: (1 << 16) // Link Write Strobe
PORTSC_CSC: (1 << 17) // Connect Status Change
PORTSC_PEC: (1 << 18) // Port Enable/Disable Change
PORTSC_WRC: (1 << 19) // Warm Port Reset Change
PORTSC_OCC: (1 << 20) // Over-current Change
PORTSC_PRC: (1 << 21) // Port Reset Change
PORTSC_PLC: (1 << 22) // Port Link State Change
PORTSC_CEC: (1 << 23) // Port Config Error Change
PORTSC_PLS_POLLING: 7
PORTSC_PLS_U0: 0
PORTSC_PLS_U2: 2
PORTSC_PLS_U3: 3
PORTSC_PLS_RXDETECT: 5
PORTSC_IND: (1 << 24) // Port Indicator Control
PORTSC_LWS_BIT: (1 << 16) // Link Write Strobe
PORTSC_DR: (1 << 30) // Device Removable
PORTSC_WPR: (1u << 31) // Warm Port Reset
PORT_SPEED_FULL: 1 // USB 1.1 Full Speed
PORT_SPEED_LOW: 2 // USB 1.1 Low Speed
PORT_SPEED_HIGH: 3 // USB 2.0 High Speed
PORT_SPEED_SUPER: 4 // USB 3.0 SuperSpeed
PORT_SPEED_SUPER_PLUS: 5 // USB 3.1 Gen2 (SuperSpeed+)
CC_SUCCESS: 1
CC_DATA_BUFFER_ERROR: 2
CC_BABBLE_DETECTED: 3
CC_USB_TRANSACTION_ERROR: 4
CC_TRB_ERROR: 5
CC_STALL_ERROR: 6
CC_RESOURCE_ERROR: 7
CC_BANDWIDTH_ERROR: 8
CC_NO_SLOTS_AVAILABLE: 9
CC_INVALID_STREAM_TYPE: 10
CC_SLOT_NOT_ENABLED_ERROR: 11
CC_ENDPOINT_NOT_ENABLED: 12
CC_SHORT_PACKET: 13
CC_RING_UNDERRUN: 14
CC_RING_OVERRUN: 15
CC_VF_EVENT_RING_FULL_ERROR: 16
CC_PARAMETER_ERROR: 17
CC_BANDWIDTH_OVERRUN_ERROR: 18
CC_CONTEXT_STATE_ERROR: 19
CC_NO_PING_RESPONSE_ERROR: 20
CC_EVENT_RING_FULL: 21
CC_INCOMPATIBLE_DEVICE: 22
CC_MISSED_SERVICE: 23
CC_COMMAND_RING_STOPPED: 24
CC_COMMAND_ABORTED: 25
CC_STOPPED: 26
CC_STOPPED_LEN_INVALID: 27
CC_STOPPED_SHORT_PACKET: 28
CC_MAX_EXIT_LATENCY_TOO_LARGE: 29
XHCI_ERDP_EHB_BIT: (1 << 3)

xHCI

include/drivers/xhci.h

struct xhci_cap_regs

struct xhci_port_regs

struct xhci_usbcmd

struct xhci_slot_ctx

struct xhci_ep_ctx

struct xhci_input_ctrl_ctx

struct xhci_input_ctx

struct xhci_device_ctx

struct xhci_op_regs

struct xhci_trb

struct xhci_ring

struct xhci_erst_entry

struct xhci_interrupter_regs

struct xhci_dcbaa

struct xhci_ext_cap

struct xhci_slot

struct xhci_port

struct xhci_device

struct xhci_command

struct xhci_request

struct xhci_return

enum xhci_slot_state

enum xhci_port_state

enum xhci_request_status

enum xhci_request_list