xHCI
| Member Type | Member Name |
|---|---|
uint8_t | cap_length |
uint8_t | reserved |
uint16_t | hci_version |
uint32_t | hcs_params1 |
uint32_t | hcs_params2 |
uint32_t | hcs_params3 |
uint32_t | hcc_params1 |
uint32_t | dboff |
uint32_t | rtsoff |
uint32_t | hcc_params2 |
| Member Type | Member Name |
|---|---|
uint32_t | portsc |
uint32_t | portpmsc |
uint32_t | portli |
uint32_t | portct |
| Member Type | Member Name |
|---|---|
union { uint32_t raw; struct { uint32_t run_stop : 1; uint32_t host_controller_reset : 1; uint32_t interrupter_enable : 1; uint32_t host_system_error_en : 1; uint32_t reserved0 : 3; uint32_t light_host_controller_reset : 1; uint32_t controller_save_state : 1; uint32_t controller_restore_state : 1; uint32_t enable_wrap_event : 1; uint32_t enable_u3_mf_index : 1; uint32_t reserved1 : 1; uint32_t cem_enable : 1; uint32_t extended_tbc_enable : 1; uint32_t extended_tbc_trb_status_enable : 1; uint32_t vtio_enable : 1; uint32_t reserved2 : 15; }; } | None |
| Member Type | Member Name |
|---|---|
uint32_t | route_string |
uint32_t | speed |
uint32_t | reserved0 |
uint32_t | mtt |
uint32_t | hub |
uint32_t | context_entries |
uint32_t | max_exit_latency |
uint32_t | root_hub_port |
uint32_t | num_ports |
uint32_t | parent_hub_slot_id |
uint32_t | parent_port_number |
uint32_t | parent_think_time |
uint32_t | reserved1 |
uint32_t | interrupter_target |
uint32_t | usb_device_address |
uint32_t | reserved2 |
uint32_t | slot_state |
uint32_t | reserved3[4] |
| Member Type | Member Name |
|---|---|
uint32_t | ep_state |
uint32_t | reserved1 |
uint32_t | mult |
uint32_t | max_pstreams |
uint32_t | lsa |
uint32_t | interval |
uint32_t | max_esit_payload_hi |
uint32_t | reserved2 |
uint32_t | error_count |
uint32_t | ep_type |
uint32_t | reserved3 |
uint32_t | host_initiate_disable |
uint32_t | max_burst_size |
uint32_t | max_packet_size |
union { uint64_t dequeue_ptr_raw; struct { uint32_t dcs : 1; /* Dequeue cycle state - value of the xHC CCS * (Consumer Cycle State) flag for the TRB * referenced by the TR Dequeue pointer. * '0' if max_pstreams > '0' */ uint32_t reserved4 : 3; uint64_t dequeue_ptr : 60; /* dequeue pointer * MUST be aligned to 16 BYTE BOUNDARY */ }; } | None |
uint32_t | average_trb_length |
uint32_t | max_esit_payload_lo |
uint32_t | reserved5[3] |
| Member Type | Member Name |
|---|---|
uint32_t | drop_flags |
uint32_t | add_flags |
uint32_t | reserved[5] |
uint32_t | config |
uint32_t | interface_num |
uint32_t | alternate_setting |
uint32_t | reserved1 |
| Member Type | Member Name |
|---|---|
struct xhci_input_ctrl_ctx | ctrl_ctx |
struct xhci_slot_ctx | slot_ctx |
struct xhci_ep_ctx | ep_ctx[31] |
| Member Type | Member Name |
|---|---|
struct xhci_slot_ctx | slot_ctx |
struct xhci_ep_ctx | ep_ctx[32] |
| Member Type | Member Name |
|---|---|
struct xhci_usbcmd | usbcmd |
uint32_t | usbsts |
uint32_t | pagesize |
uint32_t | reserved[2] |
uint32_t | dnctrl |
uint64_t | crcr |
uint32_t | reserved2[4] |
uint64_t | dcbaap |
uint32_t | config |
uint32_t | reserved3[241] |
struct xhci_port_regs | regs[] |
| Member Type | Member Name |
|---|---|
uint64_t | parameter |
uint32_t | status |
uint32_t | control |
| Member Type | Member Name |
|---|---|
struct xhci_trb | *trbs |
uint64_t | phys |
uint32_t | enqueue_index |
uint32_t | dequeue_index |
uint8_t | cycle |
uint32_t | size |
| Member Type | Member Name |
|---|---|
uint64_t | ring_segment_base |
uint32_t | ring_segment_size |
uint32_t | reserved |
| Member Type | Member Name |
|---|---|
union { uint64_t raw; struct { uint64_t desi : 3; /* Dequeue ERST Segment Index */ uint64_t ehb : 1; /* Event Handler Busy */ uint64_t event_ring_pointer : 60; }; } | None |
| Member Type | Member Name |
|---|---|
uint32_t | iman |
uint32_t | imod |
uint32_t | erstsz |
uint32_t | reserved |
uint64_t | erstba |
union { struct xhci_erdp erdp; uint64_t erdp_raw; } | None |
| Member Type | Member Name |
|---|---|
bool | device_connected |
uint8_t | speed |
uint8_t | slot_id |
bool | usb3 |
struct xhci_ring | *ep_rings[32] |
| Member Type | Member Name |
|---|---|
uint64_t | ptrs[256] |
| Member Type | Member Name |
|---|---|
uint8_t | cap_id |
uint8_t | next |
uint16_t | cap_specific |
voidxhci_init(uint8_t bus,uint8_t slot,uint8_t func,struct pci_device*dev)void *xhci_map_mmio(uint8_t bus,uint8_t slot,uint8_t func)struct xhci_device *xhci_device_create(void *mmio)boolxhci_controller_stop(struct xhci_device*dev)boolxhci_controller_reset(struct xhci_device*dev)boolxhci_controller_start(struct xhci_device*dev)voidxhci_controller_enable_ints(struct xhci_device*dev)voidxhci_setup_event_ring(struct xhci_device*dev)voidxhci_setup_command_ring(struct xhci_device*dev)boolxhci_submit_interrupt_transfer(struct usb_device*dev,struct usb_packet*packet)voidxhci_send_command(struct xhci_device*dev,uint64_t parameter,uint32_t control)uint64_txhci_wait_for_response(struct xhci_device*dev)boolxhci_wait_for_transfer_event(struct xhci_device*dev,uint8_t slot_id)uint8_txhci_enable_slot(struct xhci_device*dev)voidxhci_parse_ext_caps(struct xhci_device*dev)boolxhci_reset_port(struct xhci_device*dev,uint32_t port_index)voidxhci_detect_usb3_ports(struct xhci_device*dev)
Defines
Section titled “Defines”XHCI_DEVICE_TIMEOUT:1000TRB_RING_SIZE:256XHCI_ENDPOINT_TYPE_INVAL:0XHCI_ENDPOINT_TYPE_ISOCH_OUT:1XHCI_ENDPOINT_TYPE_BULK_OUT:2XHCI_ENDPOINT_TYPE_INTERRUPT_OUT:3XHCI_ENDPOINT_TYPE_CONTROL_BI:4XHCI_ENDPOINT_TYPE_ISOCH_IN:5XHCI_ENDPOINT_TYPE_BULK_IN:6XHCI_ENDPOINT_TYPE_INTERRUPT_IN:7XHCI_EXT_CAP_ID_LEGACY_SUPPORT:1XHCI_EXT_CAP_ID_USB:2TRB_TYPE_RESERVED:0x00TRB_TYPE_NORMAL:0x01TRB_TYPE_SETUP_STAGE:0x02TRB_TYPE_DATA_STAGE:0x03TRB_TYPE_STATUS_STAGE:0x04TRB_TYPE_ISOCH:0x05TRB_TYPE_LINK:0x06TRB_TYPE_EVENT_DATA:0x07TRB_TYPE_NO_OP:0x08TRB_TYPE_NO_OP_COMMAND:0x8TRB_TYPE_ENABLE_SLOT:0x09TRB_TYPE_DISABLE_SLOT:0x0ATRB_TYPE_ADDRESS_DEVICE:0x0BTRB_TYPE_CONFIGURE_ENDPOINT:0x0CTRB_TYPE_EVALUATE_CONTEXT:0x0DTRB_TYPE_RESET_ENDPOINT:0x0ETRB_TYPE_STOP_ENDPOINT:0x0FTRB_TYPE_SET_TR_DEQUEUE_POINTER:0x10TRB_TYPE_RESET_DEVICE:0x11TRB_TYPE_FORCE_EVENT:0x12TRB_TYPE_NEGOTIATE_BW:0x13TRB_TYPE_SET_LATENCY_TOLERANCE:0x14TRB_TYPE_GET_PORT_BANDWIDTH:0x15TRB_TYPE_FORCE_HEADER:0x16TRB_TYPE_NO_OP_2_COMMAND:0x17TRB_TYPE_TRANSFER_EVENT:0x20TRB_TYPE_COMMAND_COMPLETION:0x21TRB_TYPE_PORT_STATUS_CHANGE:0x22TRB_TYPE_BANDWIDTH_REQUEST:0x23TRB_TYPE_DOORBELL_EVENT:0x24TRB_TYPE_HOST_CONTROLLER_EVENT:0x25TRB_TYPE_DEVICE_NOTIFICATION:0x26TRB_TYPE_MFINDEX_WRAP:0x27TRB_CYCLE_BIT:(1 << 0)TRB_ENT_BIT:(1 << 1) // Evaluate Next TRBTRB_ISP_BIT:(1 << 2) // Interrupt on Short PacketTRB_NS_BIT:(1 << 3) // No SnoopTRB_CH_BIT:(1 << 4) // ChainTRB_IOC_BIT:(1 << 5) // Interrupt On CompletionTRB_IDT_BIT:(1 << 6) // Immediate DataTRB_BEI_BIT:(1 << 9) // Block Event Interrupt (ISO)TRB_TYPE_SHIFT:10PORTSC_CCS:(1 << 0) // Current Connect StatusPORTSC_PED:(1 << 1) // Port Enabled/DisabledPORTSC_OCA:(1 << 3) // Over-Current ActivePORTSC_RESET:(1 << 4) // Port ResetPORTSC_PLSE:(1 << 5) // Port Link State EnablePORTSC_PRES:(1 << 6) // Port ResumePORTSC_PP:(1 << 9) // Port PowerPORTSC_SPEED_MASK:(0xF << 10) // Bits 10–13: Port SpeedPORTSC_SPEED_SHIFT:10PORTSC_PLS_SHIFT:5PORTSC_PLS_MASK:(0xF << 5)PORTSC_LWS:(1 << 16) // Link Write StrobePORTSC_CSC:(1 << 17) // Connect Status ChangePORTSC_PEC:(1 << 18) // Port Enable/Disable ChangePORTSC_WRC:(1 << 19) // Warm Port Reset ChangePORTSC_OCC:(1 << 20) // Over-current ChangePORTSC_PRC:(1 << 21) // Port Reset ChangePORTSC_PLC:(1 << 22) // Port Link State ChangePORTSC_CEC:(1 << 23) // Port Config Error ChangePORTSC_PLS_POLLING:7PORTSC_PLS_U0:0PORTSC_PLS_U2:2PORTSC_PLS_U3:3PORTSC_PLS_RXDETECT:5PORTSC_IND:(1 << 24) // Port Indicator ControlPORTSC_LWS_BIT:(1 << 16) // Link Write StrobePORTSC_DR:(1 << 30) // Device RemovablePORTSC_WPR:(1u << 31) // Warm Port ResetPORT_SPEED_FULL:1 // USB 1.1 Full SpeedPORT_SPEED_LOW:2 // USB 1.1 Low SpeedPORT_SPEED_HIGH:3 // USB 2.0 High SpeedPORT_SPEED_SUPER:4 // USB 3.0 SuperSpeedPORT_SPEED_SUPER_PLUS:5 // USB 3.1 Gen2 (SuperSpeed+)CC_SUCCESS:0x01CC_DATA_BUFFER_ERROR:0x02CC_BABBLE_DETECTED:0x03CC_USB_TRANSACTION_ERROR:0x04CC_TRB_ERROR:0x05CC_STALL_ERROR:0x06CC_RESOURCE_ERROR:0x07CC_BANDWIDTH_ERROR:0x08CC_NO_SLOTS_AVAILABLE:0x09CC_INVALID_STREAM_TYPE:0x0ACC_SLOT_NOT_ENABLED_ERROR:0x0BXHCI_INTERRUPTER_INTERRUPT_PENDING:1XHCI_INTERRUPTER_INTERRUPT_ENABLE:(1 << 1)