LAPIC

include/acpi/lapic.h

• static inline uint32_t lapic_reg_to_x2apic_msr(uint32_t reg)
• static inline void lapic_write(uint32_t reg,uint32_t val)
• static inline uint32_t lapic_read(uint32_t reg)
• void lapic_init()
• void lapic_timer_init(uint64_t core_id)
• uint64_t lapic_get_id(void)
• uint32_t cpu_get_this_id(void)
• void lapic_timer_disable()
• bool lapic_timer_is_enabled()
• void lapic_timer_enable()
• void lapic_timer_set_ms(uint32_t ms)
• void ipi_send(uint32_t apic_id,uint8_t vector)
• void panic_broadcast(uint64_t exclude_core)
• void x2apic_init()

Defines

• LAPIC_ICR_LOW: 0x300
• LAPIC_ICR_HIGH: 0x310
• LAPIC_DELIVERY_FIXED: (0x0 << 8)
• LAPIC_DELIVERY_LOWEST: (0x1 << 8)
• LAPIC_DELIVERY_SMI: (0x2 << 8)
• LAPIC_DELIVERY_NMI: (0x4 << 8)
• LAPIC_DELIVERY_INIT: (0x5 << 8)
• LAPIC_DELIVERY_STARTUP: (0x6 << 8)
• LAPIC_LEVEL_ASSERT: (1 << 14)
• LAPIC_TRIGGER_EDGE: (0 << 15)
• LAPIC_TRIGGER_LEVEL: (1 << 15)
• LAPIC_DEST_PHYSICAL: (0 << 11)
• LAPIC_DEST_LOGICAL: (1 << 11)
• LAPIC_DEST_SHIFT: 24
• LAPIC_REG_ID: 0x020
• LAPIC_REG_EOI: 0x0B0
• LAPIC_REG_SVR: 0x0F0
• LAPIC_REG_LVT_TIMER: 0x320
• LAPIC_REG_TIMER_INIT: 0x380
• LAPIC_REG_TIMER_CUR: 0x390
• LAPIC_REG_TIMER_DIV: 0x3E0
• LAPIC_LVT_MASK: (1 << 16)
• LAPIC_ENABLE: 0x100
• LAPIC_SPURIOUS_REGISTER: 0xF0
• IA32_X2APIC_BASE: 0x800
• IA32_X2APIC_ID: (IA32_X2APIC_BASE + 0x02)
• IA32_X2APIC_EOI: (IA32_X2APIC_BASE + 0x0B)
• IA32_X2APIC_SVR: (IA32_X2APIC_BASE + 0x0F)
• IA32_X2APIC_LVT_TIMER: (IA32_X2APIC_BASE + 0x32)
• IA32_X2APIC_TIMER_INIT: (IA32_X2APIC_BASE + 0x38)
• IA32_X2APIC_TIMER_CUR: (IA32_X2APIC_BASE + 0x39)
• IA32_X2APIC_TIMER_DIV: (IA32_X2APIC_BASE + 0x3E)
• TIMER_VECTOR: 0x20
• TIMER_MODE_PERIODIC: (1 << 17)
• IA32_APIC_BASE: 0x1B
• APIC_X2APIC_ENABLE: (1 << 10)
• IA32_X2APIC_ICR: 0x830
• LAPIC_LEVEL_ASSERT: (1 << 14)
• IA32_APIC_BASE_MSR: 0x1B
• IA32_APIC_BASE_MASK: 0xFFFFF000UL
• IA32_APIC_BASE_ENABLE: (1 << 11)

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