LAPIC
uint32_t lapic_reg_to_x2apic_msr(uint32_t reg);void lapic_write(uint32_t reg, uint32_t val);uint32_t lapic_read(uint32_t reg);Defines
Section titled “Defines”#define LAPIC_ICR_LOW 0x300#define LAPIC_ICR_HIGH 0x310#define LAPIC_DELIVERY_FIXED (0x0 << 8)#define LAPIC_DELIVERY_LOWEST (0x1 << 8)#define LAPIC_DELIVERY_SMI (0x2 << 8)#define LAPIC_DELIVERY_NMI (0x4 << 8)#define LAPIC_DELIVERY_INIT (0x5 << 8)#define LAPIC_DELIVERY_STARTUP (0x6 << 8)#define LAPIC_LEVEL_ASSERT (1 << 14)#define LAPIC_TRIGGER_EDGE (0 << 15)#define LAPIC_TRIGGER_LEVEL (1 << 15)#define LAPIC_DEST_PHYSICAL (0 << 11)#define LAPIC_DEST_LOGICAL (1 << 11)#define LAPIC_DEST_SHIFT 24#define LAPIC_REG_ID 0x020#define LAPIC_REG_EOI 0x0B0#define LAPIC_REG_SVR 0x0F0#define LAPIC_REG_LVT_TIMER 0x320#define LAPIC_REG_TIMER_INIT 0x380#define LAPIC_REG_TIMER_CUR 0x390#define LAPIC_REG_TIMER_DIV 0x3E0#define LAPIC_LVT_MASK (1 << 16)#define LAPIC_ENABLE 0x100#define LAPIC_SPURIOUS_REGISTER 0xF0#define IA32_X2APIC_BASE 0x800#define IA32_X2APIC_ID (IA32_X2APIC_BASE + 0x02)#define IA32_X2APIC_EOI (IA32_X2APIC_BASE + 0x0B)#define IA32_X2APIC_SVR (IA32_X2APIC_BASE + 0x0F)#define IA32_X2APIC_LVT_TIMER (IA32_X2APIC_BASE + 0x32)#define IA32_X2APIC_TIMER_INIT (IA32_X2APIC_BASE + 0x38)#define IA32_X2APIC_TIMER_CUR (IA32_X2APIC_BASE + 0x39)#define IA32_X2APIC_TIMER_DIV (IA32_X2APIC_BASE + 0x3E)#define TIMER_VECTOR 0x20#define TIMER_MODE_PERIODIC (1 << 17)#define IA32_APIC_BASE 0x1B#define APIC_X2APIC_ENABLE (1 << 10)#define IA32_X2APIC_ICR 0x830#define LAPIC_LEVEL_ASSERT (1 << 14)#define IA32_APIC_BASE_MSR 0x1B#define IA32_APIC_BASE_MASK 0xFFFFF000UL#define IA32_APIC_BASE_ENABLE (1 << 11)