| 1 | #include <uacpi/types.h> |
| 2 | |
| 3 | /** |
| 4 | * BEFORE YOU USE THIS API: |
| 5 | * uACPI manages FADT registers on its own entirely, you should only use this |
| 6 | * API directly if there's absolutely no other way for your use case, e.g. |
| 7 | * implementing a CPU idle state driver that does C state switching or similar. |
| 8 | */ |
| 9 | |
| 10 | #ifdef __cplusplus |
| 11 | extern "C" { |
| 12 | #endif |
| 13 | |
| 14 | #ifndef UACPI_BAREBONES_MODE |
| 15 | |
| 16 | typedef enum uacpi_register { |
| 17 | UACPI_REGISTER_PM1_STS = 0, |
| 18 | UACPI_REGISTER_PM1_EN, |
| 19 | UACPI_REGISTER_PM1_CNT, |
| 20 | UACPI_REGISTER_PM_TMR, |
| 21 | UACPI_REGISTER_PM2_CNT, |
| 22 | UACPI_REGISTER_SLP_CNT, |
| 23 | UACPI_REGISTER_SLP_STS, |
| 24 | UACPI_REGISTER_RESET, |
| 25 | UACPI_REGISTER_SMI_CMD, |
| 26 | UACPI_REGISTER_MAX = UACPI_REGISTER_SMI_CMD, |
| 27 | } uacpi_register; |
| 28 | |
| 29 | /** |
| 30 | * Read a register from FADT |
| 31 | * |
| 32 | * NOTE: write-only bits (if any) are cleared automatically |
| 33 | */ |
| 34 | uacpi_status uacpi_read_register(uacpi_register, uacpi_u64*); |
| 35 | |
| 36 | /** |
| 37 | * Write a register from FADT |
| 38 | * |
| 39 | * NOTE: |
| 40 | * - Preserved bits (if any) are preserved automatically |
| 41 | * - If a register is made up of two (e.g. PM1a and PM1b) parts, the input |
| 42 | * is written to both at the same time |
| 43 | */ |
| 44 | uacpi_status uacpi_write_register(uacpi_register, uacpi_u64); |
| 45 | |
| 46 | /** |
| 47 | * Write a register from FADT |
| 48 | * |
| 49 | * NOTE: |
| 50 | * - Preserved bits (if any) are preserved automatically |
| 51 | * - For registers that are made up of two (e.g. PM1a and PM1b) parts, the |
| 52 | * provided values are written to their respective physical register |
| 53 | */ |
| 54 | uacpi_status uacpi_write_registers(uacpi_register, uacpi_u64, uacpi_u64); |
| 55 | |
| 56 | typedef enum uacpi_register_field { |
| 57 | UACPI_REGISTER_FIELD_TMR_STS = 0, |
| 58 | UACPI_REGISTER_FIELD_BM_STS, |
| 59 | UACPI_REGISTER_FIELD_GBL_STS, |
| 60 | UACPI_REGISTER_FIELD_PWRBTN_STS, |
| 61 | UACPI_REGISTER_FIELD_SLPBTN_STS, |
| 62 | UACPI_REGISTER_FIELD_RTC_STS, |
| 63 | UACPI_REGISTER_FIELD_PCIEX_WAKE_STS, |
| 64 | UACPI_REGISTER_FIELD_HWR_WAK_STS, |
| 65 | UACPI_REGISTER_FIELD_WAK_STS, |
| 66 | UACPI_REGISTER_FIELD_TMR_EN, |
| 67 | UACPI_REGISTER_FIELD_GBL_EN, |
| 68 | UACPI_REGISTER_FIELD_PWRBTN_EN, |
| 69 | UACPI_REGISTER_FIELD_SLPBTN_EN, |
| 70 | UACPI_REGISTER_FIELD_RTC_EN, |
| 71 | UACPI_REGISTER_FIELD_PCIEXP_WAKE_DIS, |
| 72 | UACPI_REGISTER_FIELD_SCI_EN, |
| 73 | UACPI_REGISTER_FIELD_BM_RLD, |
| 74 | UACPI_REGISTER_FIELD_GBL_RLS, |
| 75 | UACPI_REGISTER_FIELD_SLP_TYP, |
| 76 | UACPI_REGISTER_FIELD_HWR_SLP_TYP, |
| 77 | UACPI_REGISTER_FIELD_SLP_EN, |
| 78 | UACPI_REGISTER_FIELD_HWR_SLP_EN, |
| 79 | UACPI_REGISTER_FIELD_ARB_DIS, |
| 80 | UACPI_REGISTER_FIELD_MAX = UACPI_REGISTER_FIELD_ARB_DIS, |
| 81 | } uacpi_register_field; |
| 82 | |
| 83 | /** |
| 84 | * Read a field from a FADT register |
| 85 | * |
| 86 | * NOTE: The value is automatically masked and shifted down as appropriate, |
| 87 | * the client code doesn't have to do any bit manipulation. E.g. for |
| 88 | * a field at 0b???XX??? the returned value will contain just the 0bXX |
| 89 | */ |
| 90 | uacpi_status uacpi_read_register_field(uacpi_register_field, uacpi_u64*); |
| 91 | |
| 92 | /** |
| 93 | * Write to a field of a FADT register |
| 94 | * |
| 95 | * NOTE: The value is automatically masked and shifted up as appropriate, |
| 96 | * the client code doesn't have to do any bit manipulation. E.g. for |
| 97 | * a field at 0b???XX??? the passed value should be just 0bXX |
| 98 | */ |
| 99 | uacpi_status uacpi_write_register_field(uacpi_register_field, uacpi_u64); |
| 100 | |
| 101 | #endif // !UACPI_BAREBONES_MODE |
| 102 | |
| 103 | #ifdef __cplusplus |
| 104 | } |
| 105 | #endif |
| 106 | |