| 1 | #include <asm.h> |
| 2 | #include <ndjson.h> |
| 3 | #include <stdatomic.h> |
| 4 | #include <sync/raw_spinlock.h> |
| 5 | |
| 6 | #include "internal.h" |
| 7 | |
| 8 | #define UART_DATA 0 |
| 9 | #define UART_INT_ENABLE 1 |
| 10 | #define UART_FIFO_CTRL 2 |
| 11 | #define UART_LINE_CTRL 3 |
| 12 | #define UART_MODEM_CTRL 4 |
| 13 | #define UART_LINE_STATUS 5 |
| 14 | |
| 15 | #define UART_LSR_THRE 0x20 /* transmit holding register empty */ |
| 16 | #define UART_LCR_DLAB 0x80 |
| 17 | #define UART_LCR_8N1 0x03 |
| 18 | #define UART_DIVISOR 0x03 /* 38400 baud */ |
| 19 | |
| 20 | #define NDJSON_PANIC_LOCK_SPINS 1000000 |
| 21 | |
| 22 | /* Panic transport must remain usable when normal lock validation fails. */ |
| 23 | static struct raw_spinlock carrier_lock = RAW_SPINLOCK_INIT; |
| 24 | static uint16_t carrier_port; |
| 25 | static atomic_bool carrier_up; |
| 26 | static atomic_bool carrier_panicked; |
| 27 | |
| 28 | void ndjson_carrier_init(uint16_t port) { |
| 29 | outb(port: port + UART_INT_ENABLE, value: 0x00); |
| 30 | outb(port: port + UART_LINE_CTRL, UART_LCR_DLAB); |
| 31 | outb(port: port + UART_DATA, UART_DIVISOR); |
| 32 | outb(port: port + UART_INT_ENABLE, value: 0x00); |
| 33 | outb(port: port + UART_LINE_CTRL, UART_LCR_8N1); |
| 34 | outb(port: port + UART_FIFO_CTRL, value: 0xC7); |
| 35 | outb(port: port + UART_MODEM_CTRL, value: 0x0B); |
| 36 | |
| 37 | carrier_port = port; |
| 38 | atomic_store_explicit(&carrier_up, true, memory_order_release); |
| 39 | } |
| 40 | |
| 41 | void ndjson_carrier_disable(void) { |
| 42 | atomic_store_explicit(&carrier_up, false, memory_order_release); |
| 43 | } |
| 44 | |
| 45 | bool ndjson_carrier_online(void) { |
| 46 | return atomic_load_explicit(&carrier_up, memory_order_acquire); |
| 47 | } |
| 48 | |
| 49 | void ndjson_enter_panic(void) { |
| 50 | atomic_store_explicit(&carrier_panicked, true, memory_order_release); |
| 51 | raw_spin_unlock(lock: &carrier_lock); |
| 52 | } |
| 53 | |
| 54 | /* Raw spinlocks here, because if something IRQL related panics, |
| 55 | * it would not be able to use ndjson to log */ |
| 56 | bool ndjson_carrier_begin(bool *irqs_were_on) { |
| 57 | *irqs_were_on = false; |
| 58 | |
| 59 | if (!ndjson_carrier_online()) |
| 60 | return false; |
| 61 | |
| 62 | *irqs_were_on = are_interrupts_enabled(); |
| 63 | disable_interrupts(); |
| 64 | |
| 65 | if (atomic_load_explicit(&carrier_panicked, memory_order_acquire)) { |
| 66 | for (uint64_t i = 0; i < NDJSON_PANIC_LOCK_SPINS; i++) { |
| 67 | if (raw_spin_trylock(lock: &carrier_lock)) |
| 68 | break; |
| 69 | cpu_relax(); |
| 70 | } |
| 71 | return true; |
| 72 | } |
| 73 | |
| 74 | raw_spin_lock(lock: &carrier_lock); |
| 75 | return true; |
| 76 | } |
| 77 | |
| 78 | void ndjson_carrier_end(bool irqs_were_on) { |
| 79 | raw_spin_unlock(lock: &carrier_lock); |
| 80 | |
| 81 | if (irqs_were_on) |
| 82 | enable_interrupts(); |
| 83 | } |
| 84 | |
| 85 | void ndjson_carrier_putc(char c) { |
| 86 | while (!(inb(port: carrier_port + UART_LINE_STATUS) & UART_LSR_THRE)) |
| 87 | cpu_relax(); |
| 88 | |
| 89 | outb(port: carrier_port + UART_DATA, value: (uint8_t) c); |
| 90 | } |
| 91 | |
| 92 | void ndjson_carrier_write(const char *s, size_t len) { |
| 93 | for (size_t i = 0; i < len; i++) |
| 94 | ndjson_carrier_putc(c: s[i]); |
| 95 | } |
| 96 | |